2 ******************************************************************************
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3 * @file stm32f767xx.h
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4 * @author MCD Application Team
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5 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
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7 * This file contains:
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8 * - Data structures and the address mapping for all peripherals
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9 * - Peripheral's registers declarations and bits definition
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10 * - Macros to access peripheral
\92s registers hardware
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12 ******************************************************************************
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15 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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17 * Redistribution and use in source and binary forms, with or without modification,
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18 * are permitted provided that the following conditions are met:
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19 * 1. Redistributions of source code must retain the above copyright notice,
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20 * this list of conditions and the following disclaimer.
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21 * 2. Redistributions in binary form must reproduce the above copyright notice,
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22 * this list of conditions and the following disclaimer in the documentation
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23 * and/or other materials provided with the distribution.
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24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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25 * may be used to endorse or promote products derived from this software
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26 * without specific prior written permission.
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28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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39 ******************************************************************************
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42 /** @addtogroup CMSIS_Device
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46 /** @addtogroup stm32f767xx
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50 #ifndef __STM32F767xx_H
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51 #define __STM32F767xx_H
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55 #endif /* __cplusplus */
\r
57 /** @addtogroup Configuration_section_for_CMSIS
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62 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
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63 * in @ref Library_configuration_section
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67 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
\r
68 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
69 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
\r
70 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
\r
71 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
\r
72 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
\r
73 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
\r
74 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
\r
75 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
\r
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
\r
77 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
\r
78 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
\r
79 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
\r
80 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
\r
81 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
\r
82 RCC_IRQn = 5, /*!< RCC global Interrupt */
\r
83 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
\r
84 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
\r
85 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
\r
86 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
\r
87 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
\r
88 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
\r
89 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
\r
90 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
\r
91 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
\r
92 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
\r
93 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
\r
94 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
\r
95 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
\r
96 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
\r
97 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
\r
98 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
\r
99 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
\r
100 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
\r
101 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
\r
102 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
\r
103 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
\r
104 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
\r
105 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
\r
106 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
\r
107 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
\r
108 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
\r
109 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
\r
110 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
\r
111 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
\r
112 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
\r
113 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
\r
114 USART1_IRQn = 37, /*!< USART1 global Interrupt */
\r
115 USART2_IRQn = 38, /*!< USART2 global Interrupt */
\r
116 USART3_IRQn = 39, /*!< USART3 global Interrupt */
\r
117 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
\r
118 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
\r
119 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
\r
120 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
\r
121 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
\r
122 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
\r
123 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
\r
124 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
\r
125 FMC_IRQn = 48, /*!< FMC global Interrupt */
\r
126 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
\r
127 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
\r
128 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
\r
129 UART4_IRQn = 52, /*!< UART4 global Interrupt */
\r
130 UART5_IRQn = 53, /*!< UART5 global Interrupt */
\r
131 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
\r
132 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
\r
133 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
\r
134 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
\r
135 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
\r
136 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
\r
137 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
\r
138 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
\r
139 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
\r
140 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
\r
141 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
\r
142 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
\r
143 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
\r
144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
\r
145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
\r
146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
\r
147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
\r
148 USART6_IRQn = 71, /*!< USART6 global interrupt */
\r
149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
\r
150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
\r
151 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
\r
152 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
\r
153 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
\r
154 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
\r
155 DCMI_IRQn = 78, /*!< DCMI global interrupt */
\r
156 RNG_IRQn = 80, /*!< RNG global interrupt */
\r
157 FPU_IRQn = 81, /*!< FPU global interrupt */
\r
158 UART7_IRQn = 82, /*!< UART7 global interrupt */
\r
159 UART8_IRQn = 83, /*!< UART8 global interrupt */
\r
160 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
\r
161 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
\r
162 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
\r
163 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
\r
164 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
\r
165 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
\r
166 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
\r
167 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
\r
168 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
\r
169 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
\r
170 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
\r
171 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
\r
172 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
\r
173 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
\r
174 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
\r
175 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
\r
176 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
\r
177 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
\r
178 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
\r
179 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
\r
180 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
\r
181 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
\r
182 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
\r
183 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
\r
184 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
\r
192 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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194 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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195 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
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196 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
\r
197 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
198 #define __FPU_PRESENT 1 /*!< FPU present */
\r
199 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
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200 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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201 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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204 #include "system_stm32f7xx.h"
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205 #include <stdint.h>
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207 /** @addtogroup Peripheral_registers_structures
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212 * @brief Analog to Digital Converter
\r
217 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
\r
218 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
\r
219 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
\r
220 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
\r
221 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
\r
222 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
\r
223 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
\r
224 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
\r
225 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
\r
226 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
\r
227 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
\r
228 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
\r
229 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
\r
230 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
\r
231 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
\r
232 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
\r
233 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
\r
234 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
\r
235 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
\r
236 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
\r
241 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
\r
242 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
\r
243 __IO uint32_t CDR; /*!< ADC common regular data register for dual
\r
244 AND triple modes, Address offset: ADC1 base address + 0x308 */
\r
245 } ADC_Common_TypeDef;
\r
249 * @brief Controller Area Network TxMailBox
\r
254 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
\r
255 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
\r
256 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
\r
257 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
\r
258 } CAN_TxMailBox_TypeDef;
\r
261 * @brief Controller Area Network FIFOMailBox
\r
266 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
\r
267 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
\r
268 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
\r
269 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
\r
270 } CAN_FIFOMailBox_TypeDef;
\r
273 * @brief Controller Area Network FilterRegister
\r
278 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
\r
279 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
\r
280 } CAN_FilterRegister_TypeDef;
\r
283 * @brief Controller Area Network
\r
288 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
\r
289 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
\r
290 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
\r
291 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
\r
292 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
\r
293 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
\r
294 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
\r
295 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
\r
296 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
\r
297 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
\r
298 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
\r
299 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
\r
300 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
\r
301 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
\r
302 uint32_t RESERVED2; /*!< Reserved, 0x208 */
\r
303 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
\r
304 uint32_t RESERVED3; /*!< Reserved, 0x210 */
\r
305 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
\r
306 uint32_t RESERVED4; /*!< Reserved, 0x218 */
\r
307 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
\r
308 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
\r
309 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
\r
318 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
\r
319 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
\r
320 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
\r
321 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
\r
322 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
\r
323 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
\r
327 * @brief CRC calculation unit
\r
332 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
\r
333 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
\r
334 uint8_t RESERVED0; /*!< Reserved, 0x05 */
\r
335 uint16_t RESERVED1; /*!< Reserved, 0x06 */
\r
336 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
\r
337 uint32_t RESERVED2; /*!< Reserved, 0x0C */
\r
338 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
\r
339 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
\r
343 * @brief Digital to Analog Converter
\r
348 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
\r
349 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
\r
350 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
\r
351 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
\r
352 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
\r
353 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
\r
354 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
\r
355 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
\r
356 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
\r
357 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
\r
358 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
\r
359 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
\r
360 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
\r
361 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
\r
365 * @brief DFSDM module registers
\r
369 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
\r
370 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
\r
371 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
\r
372 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
\r
373 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
\r
374 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
\r
375 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
\r
376 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
\r
377 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
\r
378 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
\r
379 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
\r
380 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
\r
381 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
\r
382 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
\r
383 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
\r
384 } DFSDM_Filter_TypeDef;
\r
387 * @brief DFSDM channel configuration registers
\r
391 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
\r
392 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
\r
393 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
\r
394 short circuit detector register, Address offset: 0x08 */
\r
395 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
\r
396 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
\r
397 } DFSDM_Channel_TypeDef;
\r
405 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
\r
406 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
\r
407 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
\r
408 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
\r
417 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
\r
418 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
\r
419 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
\r
420 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
\r
421 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
\r
422 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
\r
423 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
\r
424 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
\r
425 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
\r
426 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
\r
427 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
\r
431 * @brief DMA Controller
\r
436 __IO uint32_t CR; /*!< DMA stream x configuration register */
\r
437 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
\r
438 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
\r
439 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
\r
440 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
\r
441 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
\r
442 } DMA_Stream_TypeDef;
\r
446 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
\r
447 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
\r
448 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
\r
449 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
\r
453 * @brief DMA2D Controller
\r
458 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
\r
459 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
\r
460 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
\r
461 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
\r
462 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
\r
463 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
\r
464 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
\r
465 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
\r
466 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
\r
467 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
\r
468 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
\r
469 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
\r
470 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
\r
471 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
\r
472 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
\r
473 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
\r
474 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
\r
475 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
\r
476 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
\r
477 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
\r
478 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
\r
479 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
\r
480 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
\r
485 * @brief Ethernet MAC
\r
490 __IO uint32_t MACCR;
\r
491 __IO uint32_t MACFFR;
\r
492 __IO uint32_t MACHTHR;
\r
493 __IO uint32_t MACHTLR;
\r
494 __IO uint32_t MACMIIAR;
\r
495 __IO uint32_t MACMIIDR;
\r
496 __IO uint32_t MACFCR;
\r
497 __IO uint32_t MACVLANTR; /* 8 */
\r
498 uint32_t RESERVED0[2];
\r
499 __IO uint32_t MACRWUFFR; /* 11 */
\r
500 __IO uint32_t MACPMTCSR;
\r
501 uint32_t RESERVED1;
\r
502 __IO uint32_t MACDBGR;
\r
503 __IO uint32_t MACSR; /* 15 */
\r
504 __IO uint32_t MACIMR;
\r
505 __IO uint32_t MACA0HR;
\r
506 __IO uint32_t MACA0LR;
\r
507 __IO uint32_t MACA1HR;
\r
508 __IO uint32_t MACA1LR;
\r
509 __IO uint32_t MACA2HR;
\r
510 __IO uint32_t MACA2LR;
\r
511 __IO uint32_t MACA3HR;
\r
512 __IO uint32_t MACA3LR; /* 24 */
\r
513 uint32_t RESERVED2[40];
\r
514 __IO uint32_t MMCCR; /* 65 */
\r
515 __IO uint32_t MMCRIR;
\r
516 __IO uint32_t MMCTIR;
\r
517 __IO uint32_t MMCRIMR;
\r
518 __IO uint32_t MMCTIMR; /* 69 */
\r
519 uint32_t RESERVED3[14];
\r
520 __IO uint32_t MMCTGFSCCR; /* 84 */
\r
521 __IO uint32_t MMCTGFMSCCR;
\r
522 uint32_t RESERVED4[5];
\r
523 __IO uint32_t MMCTGFCR;
\r
524 uint32_t RESERVED5[10];
\r
525 __IO uint32_t MMCRFCECR;
\r
526 __IO uint32_t MMCRFAECR;
\r
527 uint32_t RESERVED6[10];
\r
528 __IO uint32_t MMCRGUFCR;
\r
529 uint32_t RESERVED7[334];
\r
530 __IO uint32_t PTPTSCR;
\r
531 __IO uint32_t PTPSSIR;
\r
532 __IO uint32_t PTPTSHR;
\r
533 __IO uint32_t PTPTSLR;
\r
534 __IO uint32_t PTPTSHUR;
\r
535 __IO uint32_t PTPTSLUR;
\r
536 __IO uint32_t PTPTSAR;
\r
537 __IO uint32_t PTPTTHR;
\r
538 __IO uint32_t PTPTTLR;
\r
539 __IO uint32_t RESERVED8;
\r
540 __IO uint32_t PTPTSSR;
\r
541 uint32_t RESERVED9[565];
\r
542 __IO uint32_t DMABMR;
\r
543 __IO uint32_t DMATPDR;
\r
544 __IO uint32_t DMARPDR;
\r
545 __IO uint32_t DMARDLAR;
\r
546 __IO uint32_t DMATDLAR;
\r
547 __IO uint32_t DMASR;
\r
548 __IO uint32_t DMAOMR;
\r
549 __IO uint32_t DMAIER;
\r
550 __IO uint32_t DMAMFBOCR;
\r
551 __IO uint32_t DMARSWTR;
\r
552 uint32_t RESERVED10[8];
\r
553 __IO uint32_t DMACHTDR;
\r
554 __IO uint32_t DMACHRDR;
\r
555 __IO uint32_t DMACHTBAR;
\r
556 __IO uint32_t DMACHRBAR;
\r
560 * @brief External Interrupt/Event Controller
\r
565 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
\r
566 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
\r
567 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
\r
568 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
\r
569 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
\r
570 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
\r
574 * @brief FLASH Registers
\r
579 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
\r
580 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
\r
581 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
\r
582 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
\r
583 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
\r
584 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
\r
585 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
\r
591 * @brief Flexible Memory Controller
\r
596 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
\r
597 } FMC_Bank1_TypeDef;
\r
600 * @brief Flexible Memory Controller Bank1E
\r
605 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
\r
606 } FMC_Bank1E_TypeDef;
\r
609 * @brief Flexible Memory Controller Bank3
\r
614 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
\r
615 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
\r
616 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
\r
617 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
\r
618 uint32_t RESERVED0; /*!< Reserved, 0x90 */
\r
619 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
\r
620 } FMC_Bank3_TypeDef;
\r
623 * @brief Flexible Memory Controller Bank5_6
\r
628 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
\r
629 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
\r
630 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
\r
631 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
\r
632 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
\r
633 } FMC_Bank5_6_TypeDef;
\r
637 * @brief General Purpose I/O
\r
642 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
\r
643 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
\r
644 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
\r
645 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
\r
646 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
\r
647 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
\r
648 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
\r
649 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
\r
650 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
\r
654 * @brief System configuration controller
\r
659 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
\r
660 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
\r
661 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
\r
662 uint32_t RESERVED; /*!< Reserved, 0x18 */
\r
663 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
\r
664 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
\r
668 * @brief Inter-integrated Circuit Interface
\r
673 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
\r
674 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
\r
675 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
\r
676 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
\r
677 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
\r
678 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
\r
679 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
\r
680 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
\r
681 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
\r
682 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
\r
683 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
\r
687 * @brief Independent WATCHDOG
\r
692 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
\r
693 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
\r
694 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
\r
695 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
\r
696 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
\r
701 * @brief LCD-TFT Display Controller
\r
706 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
\r
707 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
\r
708 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
\r
709 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
\r
710 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
\r
711 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
\r
712 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
\r
713 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
\r
714 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
\r
715 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
\r
716 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
\r
717 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
\r
718 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
\r
719 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
\r
720 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
\r
721 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
\r
722 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
\r
726 * @brief LCD-TFT Display layer x Controller
\r
731 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
\r
732 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
\r
733 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
\r
734 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
\r
735 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
\r
736 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
\r
737 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
\r
738 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
\r
739 uint32_t RESERVED0[2]; /*!< Reserved */
\r
740 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
\r
741 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
\r
742 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
\r
743 uint32_t RESERVED1[3]; /*!< Reserved */
\r
744 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
\r
746 } LTDC_Layer_TypeDef;
\r
749 * @brief Power Control
\r
754 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
\r
755 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
\r
756 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
\r
757 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
\r
762 * @brief Reset and Clock Control
\r
767 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
\r
768 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
\r
769 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
\r
770 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
\r
771 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
\r
772 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
\r
773 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
\r
774 uint32_t RESERVED0; /*!< Reserved, 0x1C */
\r
775 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
\r
776 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
\r
777 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
\r
778 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
\r
779 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
\r
780 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
\r
781 uint32_t RESERVED2; /*!< Reserved, 0x3C */
\r
782 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
\r
783 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
\r
784 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
\r
785 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
\r
786 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
\r
787 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
\r
788 uint32_t RESERVED4; /*!< Reserved, 0x5C */
\r
789 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
\r
790 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
\r
791 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
\r
792 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
\r
793 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
\r
794 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
\r
795 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
\r
796 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
\r
797 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
\r
798 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
\r
799 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
\r
804 * @brief Real-Time Clock
\r
809 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
\r
810 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
\r
811 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
\r
812 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
\r
813 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
\r
814 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
\r
815 uint32_t reserved; /*!< Reserved */
\r
816 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
\r
817 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
\r
818 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
\r
819 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
\r
820 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
\r
821 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
\r
822 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
\r
823 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
\r
824 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
\r
825 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
\r
826 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
\r
827 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
\r
828 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
\r
829 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
\r
830 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
\r
831 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
\r
832 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
\r
833 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
\r
834 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
\r
835 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
\r
836 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
\r
837 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
\r
838 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
\r
839 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
\r
840 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
\r
841 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
\r
842 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
\r
843 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
\r
844 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
\r
845 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
\r
846 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
\r
847 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
\r
848 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
\r
849 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
\r
850 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
\r
851 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
\r
852 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
\r
853 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
\r
854 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
\r
855 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
\r
856 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
\r
857 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
\r
858 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
\r
859 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
\r
860 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
\r
865 * @brief Serial Audio Interface
\r
870 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
\r
875 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
\r
876 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
\r
877 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
\r
878 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
\r
879 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
\r
880 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
\r
881 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
\r
882 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
\r
883 } SAI_Block_TypeDef;
\r
886 * @brief SPDIF-RX Interface
\r
891 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
\r
892 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
\r
893 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
\r
894 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
\r
895 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
\r
896 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
\r
897 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
\r
901 * @brief SD host Interface
\r
906 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
\r
907 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
\r
908 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
\r
909 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
\r
910 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
\r
911 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
\r
912 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
\r
913 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
\r
914 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
\r
915 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
\r
916 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
\r
917 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
\r
918 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
\r
919 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
\r
920 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
\r
921 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
\r
922 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
\r
923 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
\r
924 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
\r
925 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
\r
929 * @brief Serial Peripheral Interface
\r
934 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
\r
935 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
\r
936 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
\r
937 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
\r
938 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
\r
939 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
\r
940 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
\r
941 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
\r
942 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
\r
946 * @brief QUAD Serial Peripheral Interface
\r
951 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
\r
952 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
\r
953 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
\r
954 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
\r
955 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
\r
956 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
\r
957 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
\r
958 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
\r
959 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
\r
960 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
\r
961 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
\r
962 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
\r
963 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
\r
972 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
\r
973 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
\r
974 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
\r
975 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
\r
976 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
\r
977 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
\r
978 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
\r
979 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
\r
980 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
\r
981 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
\r
982 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
\r
983 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
\r
984 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
\r
985 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
\r
986 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
\r
987 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
\r
988 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
\r
989 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
\r
990 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
\r
991 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
\r
992 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
\r
993 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
\r
994 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
\r
995 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
\r
996 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
\r
997 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
\r
1002 * @brief LPTIMIMER
\r
1006 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
\r
1007 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
\r
1008 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
\r
1009 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
\r
1010 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
\r
1011 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
\r
1012 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
\r
1013 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
\r
1018 * @brief Universal Synchronous Asynchronous Receiver Transmitter
\r
1023 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
\r
1024 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
\r
1025 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
\r
1026 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
\r
1027 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
\r
1028 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
\r
1029 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
\r
1030 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
\r
1031 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
\r
1032 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
\r
1033 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
\r
1038 * @brief Window WATCHDOG
\r
1043 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
\r
1044 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
\r
1045 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
\r
1055 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
\r
1056 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
\r
1057 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
\r
1065 * @brief USB_OTG_Core_Registers
\r
1069 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
\r
1070 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
\r
1071 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
\r
1072 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
\r
1073 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
\r
1074 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
\r
1075 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
\r
1076 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
\r
1077 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
\r
1078 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
\r
1079 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
\r
1080 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
\r
1081 uint32_t Reserved30[2]; /*!< Reserved 030h */
\r
1082 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
\r
1083 __IO uint32_t CID; /*!< User ID Register 03Ch */
\r
1084 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
\r
1085 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
\r
1086 uint32_t Reserved6; /*!< Reserved 050h */
\r
1087 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
\r
1088 uint32_t Reserved7; /*!< Reserved 058h */
\r
1089 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
\r
1090 uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */
\r
1091 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
\r
1092 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
\r
1093 } USB_OTG_GlobalTypeDef;
\r
1097 * @brief USB_OTG_device_Registers
\r
1101 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
\r
1102 __IO uint32_t DCTL; /*!< dev Control Register 804h */
\r
1103 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
\r
1104 uint32_t Reserved0C; /*!< Reserved 80Ch */
\r
1105 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
\r
1106 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
\r
1107 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
\r
1108 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
\r
1109 uint32_t Reserved20; /*!< Reserved 820h */
\r
1110 uint32_t Reserved9; /*!< Reserved 824h */
\r
1111 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
\r
1112 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
\r
1113 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
\r
1114 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
\r
1115 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
\r
1116 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
\r
1117 uint32_t Reserved40; /*!< dedicated EP mask 840h */
\r
1118 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
\r
1119 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
\r
1120 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
\r
1121 } USB_OTG_DeviceTypeDef;
\r
1125 * @brief USB_OTG_IN_Endpoint-Specific_Register
\r
1129 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
\r
1130 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
\r
1131 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
\r
1132 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
\r
1133 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
\r
1134 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
\r
1135 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
\r
1136 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
\r
1137 } USB_OTG_INEndpointTypeDef;
\r
1141 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
\r
1145 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
\r
1146 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
\r
1147 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
\r
1148 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
\r
1149 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
\r
1150 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
\r
1151 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
\r
1152 } USB_OTG_OUTEndpointTypeDef;
\r
1156 * @brief USB_OTG_Host_Mode_Register_Structures
\r
1160 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
\r
1161 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
\r
1162 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
\r
1163 uint32_t Reserved40C; /*!< Reserved 40Ch */
\r
1164 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
\r
1165 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
\r
1166 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
\r
1167 } USB_OTG_HostTypeDef;
\r
1170 * @brief USB_OTG_Host_Channel_Specific_Registers
\r
1174 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
\r
1175 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
\r
1176 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
\r
1177 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
\r
1178 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
\r
1179 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
\r
1180 uint32_t Reserved[2]; /*!< Reserved */
\r
1181 } USB_OTG_HostChannelTypeDef;
\r
1187 * @brief JPEG Codec
\r
1191 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
\r
1192 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
\r
1193 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
\r
1194 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
\r
1195 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
\r
1196 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
\r
1197 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
\r
1198 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
\r
1199 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
\r
1200 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
\r
1201 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
\r
1202 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
\r
1203 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
\r
1204 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
\r
1205 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
\r
1206 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
\r
1207 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
\r
1208 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
\r
1209 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
\r
1210 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
\r
1211 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
\r
1212 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
\r
1213 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
\r
1214 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
\r
1215 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
\r
1216 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
\r
1217 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
\r
1218 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
\r
1219 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
\r
1229 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
\r
1230 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
\r
1231 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
\r
1232 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
\r
1233 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
\r
1234 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
\r
1235 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
\r
1236 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
\r
1237 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
\r
1238 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
\r
1239 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
\r
1240 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
\r
1241 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
\r
1242 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
\r
1243 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
\r
1244 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
\r
1245 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
\r
1246 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
\r
1247 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
\r
1248 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
\r
1249 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
\r
1250 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
\r
1251 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
\r
1252 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
\r
1253 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
\r
1254 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
\r
1255 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
\r
1256 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
\r
1257 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
\r
1258 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
\r
1259 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
\r
1260 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
\r
1261 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
\r
1262 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
\r
1263 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
\r
1264 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
\r
1265 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
\r
1266 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
\r
1267 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
\r
1268 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
\r
1269 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
\r
1270 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
\r
1271 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
\r
1272 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
\r
1273 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
\r
1274 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
\r
1275 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
\r
1276 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
\r
1277 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
\r
1278 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
\r
1279 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
\r
1280 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
\r
1281 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
\r
1282 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
\r
1283 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
\r
1284 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
\r
1285 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
\r
1286 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
\r
1287 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
\r
1288 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
\r
1289 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
\r
1290 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
\r
1291 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
\r
1292 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
\r
1293 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
\r
1294 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
\r
1295 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
\r
1296 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
\r
1297 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
\r
1298 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
\r
1299 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
\r
1300 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
\r
1304 /** @addtogroup Peripheral_memory_map
\r
1307 #define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
\r
1308 #define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
\r
1309 #define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
\r
1310 #define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 128KB system data RAM accessible over DTCM */
\r
1311 #define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */
\r
1312 #define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */
\r
1313 #define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */
\r
1314 #define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */
\r
1315 #define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */
\r
1316 #define SRAM1_BASE 0x20020000UL /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
\r
1317 #define SRAM2_BASE 0x2007C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
\r
1318 #define FLASH_END 0x081FFFFFUL /*!< FLASH end address */
\r
1319 #define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
\r
1320 #define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
\r
1322 /* Legacy define */
\r
1323 #define FLASH_BASE FLASHAXI_BASE
\r
1325 /*!< Peripheral memory map */
\r
1326 #define APB1PERIPH_BASE PERIPH_BASE
\r
1327 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
\r
1328 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
\r
1329 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
\r
1331 /*!< APB1 peripherals */
\r
1332 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
\r
1333 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
\r
1334 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
\r
1335 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
\r
1336 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
\r
1337 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
\r
1338 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
\r
1339 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
\r
1340 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
\r
1341 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
\r
1342 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
\r
1343 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
\r
1344 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
\r
1345 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400UL)
\r
1346 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
\r
1347 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
\r
1348 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)
\r
1349 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
\r
1350 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
\r
1351 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
\r
1352 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
\r
1353 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
\r
1354 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
\r
1355 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
\r
1356 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL)
\r
1357 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
\r
1358 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
\r
1359 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)
\r
1360 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
\r
1361 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
\r
1362 #define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
\r
1363 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
\r
1365 /*!< APB2 peripherals */
\r
1366 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
\r
1367 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
\r
1368 #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
\r
1369 #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
\r
1370 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
\r
1371 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
\r
1372 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
\r
1373 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
\r
1374 #define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
\r
1375 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
\r
1376 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
\r
1377 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
\r
1378 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
\r
1379 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
\r
1380 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
\r
1381 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
\r
1382 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
\r
1383 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
\r
1384 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
\r
1385 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
\r
1386 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
\r
1387 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
\r
1388 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
\r
1389 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
\r
1390 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
\r
1391 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
\r
1392 #define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL)
\r
1393 #define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL)
\r
1394 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400UL)
\r
1395 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
\r
1396 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
\r
1397 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
\r
1398 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
\r
1399 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
\r
1400 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
\r
1401 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
\r
1402 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
\r
1403 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
\r
1404 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
\r
1405 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
\r
1406 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
\r
1407 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800UL)
\r
1408 /*!< AHB1 peripherals */
\r
1409 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
\r
1410 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
\r
1411 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
\r
1412 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
\r
1413 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
\r
1414 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
\r
1415 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
\r
1416 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
\r
1417 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
\r
1418 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
\r
1419 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
\r
1420 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
\r
1421 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
\r
1422 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
\r
1423 #define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */
\r
1424 #define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */
\r
1425 #define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */
\r
1426 /* Legacy define */
\r
1427 #define PACKAGESIZE_BASE PACKAGE_BASE
\r
1429 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
\r
1430 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
\r
1431 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
\r
1432 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
\r
1433 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
\r
1434 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
\r
1435 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
\r
1436 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
\r
1437 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
\r
1438 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
\r
1439 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
\r
1440 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
\r
1441 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
\r
1442 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
\r
1443 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
\r
1444 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
\r
1445 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
\r
1446 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
\r
1447 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
\r
1448 #define ETH_MAC_BASE (ETH_BASE)
\r
1449 #define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
\r
1450 #define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
\r
1451 #define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
\r
1452 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
\r
1453 /*!< AHB2 peripherals */
\r
1454 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
\r
1455 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000UL)
\r
1456 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
\r
1457 /*!< FMC Bankx registers base address */
\r
1458 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
\r
1459 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
\r
1460 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
\r
1461 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
\r
1463 /* Debug MCU registers base address */
\r
1464 #define DBGMCU_BASE 0xE0042000UL
\r
1466 /*!< USB registers base address */
\r
1467 #define USB_OTG_HS_PERIPH_BASE 0x40040000UL
\r
1468 #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
\r
1470 #define USB_OTG_GLOBAL_BASE 0x0000UL
\r
1471 #define USB_OTG_DEVICE_BASE 0x0800UL
\r
1472 #define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
\r
1473 #define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
\r
1474 #define USB_OTG_EP_REG_SIZE 0x0020UL
\r
1475 #define USB_OTG_HOST_BASE 0x0400UL
\r
1476 #define USB_OTG_HOST_PORT_BASE 0x0440UL
\r
1477 #define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
\r
1478 #define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
\r
1479 #define USB_OTG_PCGCCTL_BASE 0x0E00UL
\r
1480 #define USB_OTG_FIFO_BASE 0x1000UL
\r
1481 #define USB_OTG_FIFO_SIZE 0x1000UL
\r
1487 /** @addtogroup Peripheral_declaration
\r
1490 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
\r
1491 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
\r
1492 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
\r
1493 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
\r
1494 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
\r
1495 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
\r
1496 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
\r
1497 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
\r
1498 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
\r
1499 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
\r
1500 #define RTC ((RTC_TypeDef *) RTC_BASE)
\r
1501 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
\r
1502 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
\r
1503 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
\r
1504 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
\r
1505 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
\r
1506 #define USART2 ((USART_TypeDef *) USART2_BASE)
\r
1507 #define USART3 ((USART_TypeDef *) USART3_BASE)
\r
1508 #define UART4 ((USART_TypeDef *) UART4_BASE)
\r
1509 #define UART5 ((USART_TypeDef *) UART5_BASE)
\r
1510 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
\r
1511 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
\r
1512 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
\r
1513 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
\r
1514 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
\r
1515 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
\r
1516 #define CEC ((CEC_TypeDef *) CEC_BASE)
\r
1517 #define PWR ((PWR_TypeDef *) PWR_BASE)
\r
1518 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
\r
1519 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
\r
1520 #define UART7 ((USART_TypeDef *) UART7_BASE)
\r
1521 #define UART8 ((USART_TypeDef *) UART8_BASE)
\r
1522 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
\r
1523 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
\r
1524 #define USART1 ((USART_TypeDef *) USART1_BASE)
\r
1525 #define USART6 ((USART_TypeDef *) USART6_BASE)
\r
1526 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
\r
1527 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
\r
1528 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
\r
1529 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
\r
1530 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
\r
1531 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
\r
1532 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
\r
1533 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
\r
1534 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
\r
1535 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
\r
1536 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
\r
1537 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
\r
1538 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
\r
1539 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
\r
1540 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
\r
1541 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
\r
1542 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
\r
1543 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
\r
1544 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
\r
1545 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
\r
1546 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
\r
1547 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
\r
1548 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
\r
1549 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
\r
1550 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
\r
1551 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
\r
1552 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
\r
1553 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
\r
1554 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
\r
1555 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
\r
1556 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
\r
1557 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
\r
1558 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
\r
1559 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
\r
1560 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
\r
1561 #define CRC ((CRC_TypeDef *) CRC_BASE)
\r
1562 #define RCC ((RCC_TypeDef *) RCC_BASE)
\r
1563 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
\r
1564 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
\r
1565 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
\r
1566 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
\r
1567 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
\r
1568 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
\r
1569 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
\r
1570 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
\r
1571 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
\r
1572 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
\r
1573 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
\r
1574 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
\r
1575 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
\r
1576 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
\r
1577 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
\r
1578 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
\r
1579 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
\r
1580 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
\r
1581 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
\r
1582 #define ETH ((ETH_TypeDef *) ETH_BASE)
\r
1583 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
\r
1584 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
\r
1585 #define RNG ((RNG_TypeDef *) RNG_BASE)
\r
1586 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
\r
1587 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
\r
1588 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
\r
1589 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
\r
1590 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
\r
1591 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
\r
1592 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
\r
1593 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
\r
1594 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
\r
1595 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
\r
1596 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
\r
1597 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
\r
1598 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
\r
1599 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
\r
1600 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
\r
1601 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
\r
1602 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
\r
1603 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
\r
1604 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
\r
1605 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
\r
1606 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
\r
1607 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
\r
1608 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
\r
1609 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
\r
1615 /** @addtogroup Exported_constants
\r
1619 /** @addtogroup Peripheral_Registers_Bits_Definition
\r
1623 /******************************************************************************/
\r
1624 /* Peripheral Registers_Bits_Definition */
\r
1625 /******************************************************************************/
\r
1627 /******************************************************************************/
\r
1629 /* Analog to Digital Converter */
\r
1631 /******************************************************************************/
\r
1632 /******************** Bit definition for ADC_SR register ********************/
\r
1633 #define ADC_SR_AWD_Pos (0U)
\r
1634 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
\r
1635 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
\r
1636 #define ADC_SR_EOC_Pos (1U)
\r
1637 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
\r
1638 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
\r
1639 #define ADC_SR_JEOC_Pos (2U)
\r
1640 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
\r
1641 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
\r
1642 #define ADC_SR_JSTRT_Pos (3U)
\r
1643 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
\r
1644 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
\r
1645 #define ADC_SR_STRT_Pos (4U)
\r
1646 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
\r
1647 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
\r
1648 #define ADC_SR_OVR_Pos (5U)
\r
1649 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
\r
1650 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
\r
1652 /******************* Bit definition for ADC_CR1 register ********************/
\r
1653 #define ADC_CR1_AWDCH_Pos (0U)
\r
1654 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
\r
1655 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
\r
1656 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
\r
1657 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
\r
1658 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
\r
1659 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
\r
1660 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
\r
1661 #define ADC_CR1_EOCIE_Pos (5U)
\r
1662 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
\r
1663 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
\r
1664 #define ADC_CR1_AWDIE_Pos (6U)
\r
1665 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
\r
1666 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
\r
1667 #define ADC_CR1_JEOCIE_Pos (7U)
\r
1668 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
\r
1669 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
\r
1670 #define ADC_CR1_SCAN_Pos (8U)
\r
1671 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
\r
1672 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
\r
1673 #define ADC_CR1_AWDSGL_Pos (9U)
\r
1674 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
\r
1675 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
\r
1676 #define ADC_CR1_JAUTO_Pos (10U)
\r
1677 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
\r
1678 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
\r
1679 #define ADC_CR1_DISCEN_Pos (11U)
\r
1680 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
\r
1681 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
\r
1682 #define ADC_CR1_JDISCEN_Pos (12U)
\r
1683 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
\r
1684 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
\r
1685 #define ADC_CR1_DISCNUM_Pos (13U)
\r
1686 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
\r
1687 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
\r
1688 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
\r
1689 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
\r
1690 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
\r
1691 #define ADC_CR1_JAWDEN_Pos (22U)
\r
1692 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
\r
1693 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
\r
1694 #define ADC_CR1_AWDEN_Pos (23U)
\r
1695 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
\r
1696 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
\r
1697 #define ADC_CR1_RES_Pos (24U)
\r
1698 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
\r
1699 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
\r
1700 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
\r
1701 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
\r
1702 #define ADC_CR1_OVRIE_Pos (26U)
\r
1703 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
\r
1704 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
\r
1706 /******************* Bit definition for ADC_CR2 register ********************/
\r
1707 #define ADC_CR2_ADON_Pos (0U)
\r
1708 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
\r
1709 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
\r
1710 #define ADC_CR2_CONT_Pos (1U)
\r
1711 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
\r
1712 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
\r
1713 #define ADC_CR2_DMA_Pos (8U)
\r
1714 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
\r
1715 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
\r
1716 #define ADC_CR2_DDS_Pos (9U)
\r
1717 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
\r
1718 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
\r
1719 #define ADC_CR2_EOCS_Pos (10U)
\r
1720 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
\r
1721 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
\r
1722 #define ADC_CR2_ALIGN_Pos (11U)
\r
1723 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
\r
1724 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
\r
1725 #define ADC_CR2_JEXTSEL_Pos (16U)
\r
1726 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
\r
1727 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
\r
1728 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
\r
1729 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
\r
1730 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
\r
1731 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
\r
1732 #define ADC_CR2_JEXTEN_Pos (20U)
\r
1733 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
\r
1734 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
\r
1735 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
\r
1736 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
\r
1737 #define ADC_CR2_JSWSTART_Pos (22U)
\r
1738 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
\r
1739 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
\r
1740 #define ADC_CR2_EXTSEL_Pos (24U)
\r
1741 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
\r
1742 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
\r
1743 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
\r
1744 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
\r
1745 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
\r
1746 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
\r
1747 #define ADC_CR2_EXTEN_Pos (28U)
\r
1748 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
\r
1749 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
\r
1750 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
\r
1751 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
\r
1752 #define ADC_CR2_SWSTART_Pos (30U)
\r
1753 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
\r
1754 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
\r
1756 /****************** Bit definition for ADC_SMPR1 register *******************/
\r
1757 #define ADC_SMPR1_SMP10_Pos (0U)
\r
1758 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
\r
1759 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
\r
1760 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
\r
1761 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
\r
1762 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
\r
1763 #define ADC_SMPR1_SMP11_Pos (3U)
\r
1764 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
\r
1765 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
\r
1766 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
\r
1767 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
\r
1768 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
\r
1769 #define ADC_SMPR1_SMP12_Pos (6U)
\r
1770 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
\r
1771 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
\r
1772 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
\r
1773 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
\r
1774 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
\r
1775 #define ADC_SMPR1_SMP13_Pos (9U)
\r
1776 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
\r
1777 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
\r
1778 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
\r
1779 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
\r
1780 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
\r
1781 #define ADC_SMPR1_SMP14_Pos (12U)
\r
1782 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
\r
1783 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
\r
1784 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
\r
1785 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
\r
1786 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
\r
1787 #define ADC_SMPR1_SMP15_Pos (15U)
\r
1788 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
\r
1789 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
\r
1790 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
\r
1791 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
\r
1792 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
\r
1793 #define ADC_SMPR1_SMP16_Pos (18U)
\r
1794 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
\r
1795 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
\r
1796 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
\r
1797 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
\r
1798 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
\r
1799 #define ADC_SMPR1_SMP17_Pos (21U)
\r
1800 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
\r
1801 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
\r
1802 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
\r
1803 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
\r
1804 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
\r
1805 #define ADC_SMPR1_SMP18_Pos (24U)
\r
1806 #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
\r
1807 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
\r
1808 #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
\r
1809 #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
\r
1810 #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
\r
1812 /****************** Bit definition for ADC_SMPR2 register *******************/
\r
1813 #define ADC_SMPR2_SMP0_Pos (0U)
\r
1814 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
\r
1815 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
\r
1816 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
\r
1817 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
\r
1818 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
\r
1819 #define ADC_SMPR2_SMP1_Pos (3U)
\r
1820 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
\r
1821 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
\r
1822 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
\r
1823 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
\r
1824 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
\r
1825 #define ADC_SMPR2_SMP2_Pos (6U)
\r
1826 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
\r
1827 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
\r
1828 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
\r
1829 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
\r
1830 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
\r
1831 #define ADC_SMPR2_SMP3_Pos (9U)
\r
1832 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
\r
1833 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
\r
1834 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
\r
1835 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
\r
1836 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
\r
1837 #define ADC_SMPR2_SMP4_Pos (12U)
\r
1838 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
\r
1839 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
\r
1840 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
\r
1841 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
\r
1842 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
\r
1843 #define ADC_SMPR2_SMP5_Pos (15U)
\r
1844 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
\r
1845 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
\r
1846 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
\r
1847 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
\r
1848 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
\r
1849 #define ADC_SMPR2_SMP6_Pos (18U)
\r
1850 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
\r
1851 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
\r
1852 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
\r
1853 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
\r
1854 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
\r
1855 #define ADC_SMPR2_SMP7_Pos (21U)
\r
1856 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
\r
1857 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
\r
1858 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
\r
1859 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
\r
1860 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
\r
1861 #define ADC_SMPR2_SMP8_Pos (24U)
\r
1862 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
\r
1863 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
\r
1864 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
\r
1865 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
\r
1866 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
\r
1867 #define ADC_SMPR2_SMP9_Pos (27U)
\r
1868 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
\r
1869 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
\r
1870 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
\r
1871 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
\r
1872 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
\r
1874 /****************** Bit definition for ADC_JOFR1 register *******************/
\r
1875 #define ADC_JOFR1_JOFFSET1_Pos (0U)
\r
1876 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
\r
1877 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
\r
1879 /****************** Bit definition for ADC_JOFR2 register *******************/
\r
1880 #define ADC_JOFR2_JOFFSET2_Pos (0U)
\r
1881 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
\r
1882 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
\r
1884 /****************** Bit definition for ADC_JOFR3 register *******************/
\r
1885 #define ADC_JOFR3_JOFFSET3_Pos (0U)
\r
1886 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
\r
1887 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
\r
1889 /****************** Bit definition for ADC_JOFR4 register *******************/
\r
1890 #define ADC_JOFR4_JOFFSET4_Pos (0U)
\r
1891 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
\r
1892 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
\r
1894 /******************* Bit definition for ADC_HTR register ********************/
\r
1895 #define ADC_HTR_HT_Pos (0U)
\r
1896 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
\r
1897 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
\r
1899 /******************* Bit definition for ADC_LTR register ********************/
\r
1900 #define ADC_LTR_LT_Pos (0U)
\r
1901 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
\r
1902 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
\r
1904 /******************* Bit definition for ADC_SQR1 register *******************/
\r
1905 #define ADC_SQR1_SQ13_Pos (0U)
\r
1906 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
\r
1907 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
\r
1908 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
\r
1909 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
\r
1910 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
\r
1911 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
\r
1912 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
\r
1913 #define ADC_SQR1_SQ14_Pos (5U)
\r
1914 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
\r
1915 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
\r
1916 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
\r
1917 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
\r
1918 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
\r
1919 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
\r
1920 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
\r
1921 #define ADC_SQR1_SQ15_Pos (10U)
\r
1922 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
\r
1923 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
\r
1924 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
\r
1925 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
\r
1926 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
\r
1927 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
\r
1928 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
\r
1929 #define ADC_SQR1_SQ16_Pos (15U)
\r
1930 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
\r
1931 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
\r
1932 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
\r
1933 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
\r
1934 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
\r
1935 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
\r
1936 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
\r
1937 #define ADC_SQR1_L_Pos (20U)
\r
1938 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
\r
1939 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
\r
1940 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
\r
1941 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
\r
1942 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
\r
1943 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
\r
1945 /******************* Bit definition for ADC_SQR2 register *******************/
\r
1946 #define ADC_SQR2_SQ7_Pos (0U)
\r
1947 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
\r
1948 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
\r
1949 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
\r
1950 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
\r
1951 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
\r
1952 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
\r
1953 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
\r
1954 #define ADC_SQR2_SQ8_Pos (5U)
\r
1955 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
\r
1956 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
\r
1957 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
\r
1958 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
\r
1959 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
\r
1960 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
\r
1961 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
\r
1962 #define ADC_SQR2_SQ9_Pos (10U)
\r
1963 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
\r
1964 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
\r
1965 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
\r
1966 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
\r
1967 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
\r
1968 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
\r
1969 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
\r
1970 #define ADC_SQR2_SQ10_Pos (15U)
\r
1971 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
\r
1972 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
\r
1973 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
\r
1974 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
\r
1975 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
\r
1976 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
\r
1977 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
\r
1978 #define ADC_SQR2_SQ11_Pos (20U)
\r
1979 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
\r
1980 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
\r
1981 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
\r
1982 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
\r
1983 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
\r
1984 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
\r
1985 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
\r
1986 #define ADC_SQR2_SQ12_Pos (25U)
\r
1987 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
\r
1988 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
\r
1989 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
\r
1990 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
\r
1991 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
\r
1992 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
\r
1993 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
\r
1995 /******************* Bit definition for ADC_SQR3 register *******************/
\r
1996 #define ADC_SQR3_SQ1_Pos (0U)
\r
1997 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
\r
1998 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
\r
1999 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
\r
2000 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
\r
2001 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
\r
2002 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
\r
2003 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
\r
2004 #define ADC_SQR3_SQ2_Pos (5U)
\r
2005 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
\r
2006 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
\r
2007 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
\r
2008 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
\r
2009 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
\r
2010 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
\r
2011 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
\r
2012 #define ADC_SQR3_SQ3_Pos (10U)
\r
2013 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
\r
2014 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
\r
2015 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
\r
2016 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
\r
2017 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
\r
2018 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
\r
2019 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
\r
2020 #define ADC_SQR3_SQ4_Pos (15U)
\r
2021 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
\r
2022 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
\r
2023 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
\r
2024 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
\r
2025 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
\r
2026 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
\r
2027 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
\r
2028 #define ADC_SQR3_SQ5_Pos (20U)
\r
2029 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
\r
2030 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
\r
2031 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
\r
2032 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
\r
2033 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
\r
2034 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
\r
2035 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
\r
2036 #define ADC_SQR3_SQ6_Pos (25U)
\r
2037 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
\r
2038 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
\r
2039 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
\r
2040 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
\r
2041 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
\r
2042 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
\r
2043 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
\r
2045 /******************* Bit definition for ADC_JSQR register *******************/
\r
2046 #define ADC_JSQR_JSQ1_Pos (0U)
\r
2047 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
\r
2048 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
\r
2049 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
\r
2050 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
\r
2051 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
\r
2052 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
\r
2053 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
\r
2054 #define ADC_JSQR_JSQ2_Pos (5U)
\r
2055 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
\r
2056 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
\r
2057 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
\r
2058 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
\r
2059 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
\r
2060 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
\r
2061 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
\r
2062 #define ADC_JSQR_JSQ3_Pos (10U)
\r
2063 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
\r
2064 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
\r
2065 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
\r
2066 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
\r
2067 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
\r
2068 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
\r
2069 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
\r
2070 #define ADC_JSQR_JSQ4_Pos (15U)
\r
2071 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
\r
2072 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
\r
2073 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
\r
2074 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
\r
2075 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
\r
2076 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
\r
2077 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
\r
2078 #define ADC_JSQR_JL_Pos (20U)
\r
2079 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
\r
2080 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
\r
2081 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
\r
2082 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
\r
2084 /******************* Bit definition for ADC_JDR1 register *******************/
\r
2085 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
\r
2087 /******************* Bit definition for ADC_JDR2 register *******************/
\r
2088 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
\r
2090 /******************* Bit definition for ADC_JDR3 register *******************/
\r
2091 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
\r
2093 /******************* Bit definition for ADC_JDR4 register *******************/
\r
2094 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
\r
2096 /******************** Bit definition for ADC_DR register ********************/
\r
2097 #define ADC_DR_DATA_Pos (0U)
\r
2098 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
\r
2099 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
\r
2100 #define ADC_DR_ADC2DATA_Pos (16U)
\r
2101 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
\r
2102 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
\r
2104 /******************* Bit definition for ADC_CSR register ********************/
\r
2105 #define ADC_CSR_AWD1_Pos (0U)
\r
2106 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
\r
2107 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
\r
2108 #define ADC_CSR_EOC1_Pos (1U)
\r
2109 #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
\r
2110 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
\r
2111 #define ADC_CSR_JEOC1_Pos (2U)
\r
2112 #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
\r
2113 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
\r
2114 #define ADC_CSR_JSTRT1_Pos (3U)
\r
2115 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
\r
2116 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
\r
2117 #define ADC_CSR_STRT1_Pos (4U)
\r
2118 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
\r
2119 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
\r
2120 #define ADC_CSR_OVR1_Pos (5U)
\r
2121 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
\r
2122 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
\r
2123 #define ADC_CSR_AWD2_Pos (8U)
\r
2124 #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
\r
2125 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
\r
2126 #define ADC_CSR_EOC2_Pos (9U)
\r
2127 #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
\r
2128 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
\r
2129 #define ADC_CSR_JEOC2_Pos (10U)
\r
2130 #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
\r
2131 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
\r
2132 #define ADC_CSR_JSTRT2_Pos (11U)
\r
2133 #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
\r
2134 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
\r
2135 #define ADC_CSR_STRT2_Pos (12U)
\r
2136 #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
\r
2137 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
\r
2138 #define ADC_CSR_OVR2_Pos (13U)
\r
2139 #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
\r
2140 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
\r
2141 #define ADC_CSR_AWD3_Pos (16U)
\r
2142 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
\r
2143 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
\r
2144 #define ADC_CSR_EOC3_Pos (17U)
\r
2145 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
\r
2146 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
\r
2147 #define ADC_CSR_JEOC3_Pos (18U)
\r
2148 #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
\r
2149 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
\r
2150 #define ADC_CSR_JSTRT3_Pos (19U)
\r
2151 #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
\r
2152 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
\r
2153 #define ADC_CSR_STRT3_Pos (20U)
\r
2154 #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
\r
2155 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
\r
2156 #define ADC_CSR_OVR3_Pos (21U)
\r
2157 #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
\r
2158 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
\r
2160 /* Legacy defines */
\r
2161 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
\r
2162 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
\r
2163 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
\r
2166 /******************* Bit definition for ADC_CCR register ********************/
\r
2167 #define ADC_CCR_MULTI_Pos (0U)
\r
2168 #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
\r
2169 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
\r
2170 #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
\r
2171 #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
\r
2172 #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
\r
2173 #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
\r
2174 #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
\r
2175 #define ADC_CCR_DELAY_Pos (8U)
\r
2176 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
\r
2177 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
\r
2178 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
\r
2179 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
\r
2180 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
\r
2181 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
\r
2182 #define ADC_CCR_DDS_Pos (13U)
\r
2183 #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
\r
2184 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
\r
2185 #define ADC_CCR_DMA_Pos (14U)
\r
2186 #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
\r
2187 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
\r
2188 #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
\r
2189 #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
\r
2190 #define ADC_CCR_ADCPRE_Pos (16U)
\r
2191 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
\r
2192 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
\r
2193 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
\r
2194 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
\r
2195 #define ADC_CCR_VBATE_Pos (22U)
\r
2196 #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
\r
2197 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
\r
2198 #define ADC_CCR_TSVREFE_Pos (23U)
\r
2199 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
\r
2200 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
\r
2202 /******************* Bit definition for ADC_CDR register ********************/
\r
2203 #define ADC_CDR_DATA1_Pos (0U)
\r
2204 #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
\r
2205 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
\r
2206 #define ADC_CDR_DATA2_Pos (16U)
\r
2207 #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
\r
2208 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
\r
2210 /* Legacy defines */
\r
2211 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
\r
2212 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
\r
2214 /******************************************************************************/
\r
2216 /* Controller Area Network */
\r
2218 /******************************************************************************/
\r
2219 /*!<CAN control and status registers */
\r
2220 /******************* Bit definition for CAN_MCR register ********************/
\r
2221 #define CAN_MCR_INRQ_Pos (0U)
\r
2222 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
\r
2223 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
\r
2224 #define CAN_MCR_SLEEP_Pos (1U)
\r
2225 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
\r
2226 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
\r
2227 #define CAN_MCR_TXFP_Pos (2U)
\r
2228 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
\r
2229 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
\r
2230 #define CAN_MCR_RFLM_Pos (3U)
\r
2231 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
\r
2232 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
\r
2233 #define CAN_MCR_NART_Pos (4U)
\r
2234 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
\r
2235 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
\r
2236 #define CAN_MCR_AWUM_Pos (5U)
\r
2237 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
\r
2238 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
\r
2239 #define CAN_MCR_ABOM_Pos (6U)
\r
2240 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
\r
2241 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
\r
2242 #define CAN_MCR_TTCM_Pos (7U)
\r
2243 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
\r
2244 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
\r
2245 #define CAN_MCR_RESET_Pos (15U)
\r
2246 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
\r
2247 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
\r
2249 /******************* Bit definition for CAN_MSR register ********************/
\r
2250 #define CAN_MSR_INAK_Pos (0U)
\r
2251 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
\r
2252 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
\r
2253 #define CAN_MSR_SLAK_Pos (1U)
\r
2254 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
\r
2255 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
\r
2256 #define CAN_MSR_ERRI_Pos (2U)
\r
2257 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
\r
2258 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
\r
2259 #define CAN_MSR_WKUI_Pos (3U)
\r
2260 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
\r
2261 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
\r
2262 #define CAN_MSR_SLAKI_Pos (4U)
\r
2263 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
\r
2264 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
\r
2265 #define CAN_MSR_TXM_Pos (8U)
\r
2266 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
\r
2267 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
\r
2268 #define CAN_MSR_RXM_Pos (9U)
\r
2269 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
\r
2270 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
\r
2271 #define CAN_MSR_SAMP_Pos (10U)
\r
2272 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
\r
2273 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
\r
2274 #define CAN_MSR_RX_Pos (11U)
\r
2275 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
\r
2276 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
\r
2278 /******************* Bit definition for CAN_TSR register ********************/
\r
2279 #define CAN_TSR_RQCP0_Pos (0U)
\r
2280 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
\r
2281 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
\r
2282 #define CAN_TSR_TXOK0_Pos (1U)
\r
2283 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
\r
2284 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
\r
2285 #define CAN_TSR_ALST0_Pos (2U)
\r
2286 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
\r
2287 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
\r
2288 #define CAN_TSR_TERR0_Pos (3U)
\r
2289 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
\r
2290 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
\r
2291 #define CAN_TSR_ABRQ0_Pos (7U)
\r
2292 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
\r
2293 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
\r
2294 #define CAN_TSR_RQCP1_Pos (8U)
\r
2295 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
\r
2296 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
\r
2297 #define CAN_TSR_TXOK1_Pos (9U)
\r
2298 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
\r
2299 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
\r
2300 #define CAN_TSR_ALST1_Pos (10U)
\r
2301 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
\r
2302 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
\r
2303 #define CAN_TSR_TERR1_Pos (11U)
\r
2304 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
\r
2305 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
\r
2306 #define CAN_TSR_ABRQ1_Pos (15U)
\r
2307 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
\r
2308 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
\r
2309 #define CAN_TSR_RQCP2_Pos (16U)
\r
2310 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
\r
2311 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
\r
2312 #define CAN_TSR_TXOK2_Pos (17U)
\r
2313 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
\r
2314 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
\r
2315 #define CAN_TSR_ALST2_Pos (18U)
\r
2316 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
\r
2317 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
\r
2318 #define CAN_TSR_TERR2_Pos (19U)
\r
2319 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
\r
2320 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
\r
2321 #define CAN_TSR_ABRQ2_Pos (23U)
\r
2322 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
\r
2323 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
\r
2324 #define CAN_TSR_CODE_Pos (24U)
\r
2325 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
\r
2326 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
\r
2328 #define CAN_TSR_TME_Pos (26U)
\r
2329 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
\r
2330 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
\r
2331 #define CAN_TSR_TME0_Pos (26U)
\r
2332 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
\r
2333 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
\r
2334 #define CAN_TSR_TME1_Pos (27U)
\r
2335 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
\r
2336 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
\r
2337 #define CAN_TSR_TME2_Pos (28U)
\r
2338 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
\r
2339 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
\r
2341 #define CAN_TSR_LOW_Pos (29U)
\r
2342 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
\r
2343 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
\r
2344 #define CAN_TSR_LOW0_Pos (29U)
\r
2345 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
\r
2346 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
\r
2347 #define CAN_TSR_LOW1_Pos (30U)
\r
2348 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
\r
2349 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
\r
2350 #define CAN_TSR_LOW2_Pos (31U)
\r
2351 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
\r
2352 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
\r
2354 /******************* Bit definition for CAN_RF0R register *******************/
\r
2355 #define CAN_RF0R_FMP0_Pos (0U)
\r
2356 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
\r
2357 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
\r
2358 #define CAN_RF0R_FULL0_Pos (3U)
\r
2359 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
\r
2360 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
\r
2361 #define CAN_RF0R_FOVR0_Pos (4U)
\r
2362 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
\r
2363 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
\r
2364 #define CAN_RF0R_RFOM0_Pos (5U)
\r
2365 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
\r
2366 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
\r
2368 /******************* Bit definition for CAN_RF1R register *******************/
\r
2369 #define CAN_RF1R_FMP1_Pos (0U)
\r
2370 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
\r
2371 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
\r
2372 #define CAN_RF1R_FULL1_Pos (3U)
\r
2373 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
\r
2374 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
\r
2375 #define CAN_RF1R_FOVR1_Pos (4U)
\r
2376 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
\r
2377 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
\r
2378 #define CAN_RF1R_RFOM1_Pos (5U)
\r
2379 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
\r
2380 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
\r
2382 /******************** Bit definition for CAN_IER register *******************/
\r
2383 #define CAN_IER_TMEIE_Pos (0U)
\r
2384 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
\r
2385 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
\r
2386 #define CAN_IER_FMPIE0_Pos (1U)
\r
2387 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
\r
2388 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
\r
2389 #define CAN_IER_FFIE0_Pos (2U)
\r
2390 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
\r
2391 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
\r
2392 #define CAN_IER_FOVIE0_Pos (3U)
\r
2393 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
\r
2394 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
\r
2395 #define CAN_IER_FMPIE1_Pos (4U)
\r
2396 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
\r
2397 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
\r
2398 #define CAN_IER_FFIE1_Pos (5U)
\r
2399 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
\r
2400 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
\r
2401 #define CAN_IER_FOVIE1_Pos (6U)
\r
2402 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
\r
2403 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
\r
2404 #define CAN_IER_EWGIE_Pos (8U)
\r
2405 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
\r
2406 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
\r
2407 #define CAN_IER_EPVIE_Pos (9U)
\r
2408 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
\r
2409 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
\r
2410 #define CAN_IER_BOFIE_Pos (10U)
\r
2411 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
\r
2412 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
\r
2413 #define CAN_IER_LECIE_Pos (11U)
\r
2414 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
\r
2415 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
\r
2416 #define CAN_IER_ERRIE_Pos (15U)
\r
2417 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
\r
2418 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
\r
2419 #define CAN_IER_WKUIE_Pos (16U)
\r
2420 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
\r
2421 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
\r
2422 #define CAN_IER_SLKIE_Pos (17U)
\r
2423 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
\r
2424 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
\r
2426 /******************** Bit definition for CAN_ESR register *******************/
\r
2427 #define CAN_ESR_EWGF_Pos (0U)
\r
2428 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
\r
2429 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
\r
2430 #define CAN_ESR_EPVF_Pos (1U)
\r
2431 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
\r
2432 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
\r
2433 #define CAN_ESR_BOFF_Pos (2U)
\r
2434 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
\r
2435 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
\r
2437 #define CAN_ESR_LEC_Pos (4U)
\r
2438 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
\r
2439 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
\r
2440 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
\r
2441 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
\r
2442 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
\r
2444 #define CAN_ESR_TEC_Pos (16U)
\r
2445 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
\r
2446 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
\r
2447 #define CAN_ESR_REC_Pos (24U)
\r
2448 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
\r
2449 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
\r
2451 /******************* Bit definition for CAN_BTR register ********************/
\r
2452 #define CAN_BTR_BRP_Pos (0U)
\r
2453 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
\r
2454 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
\r
2455 #define CAN_BTR_TS1_Pos (16U)
\r
2456 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
\r
2457 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
\r
2458 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
\r
2459 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
\r
2460 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
\r
2461 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
\r
2462 #define CAN_BTR_TS2_Pos (20U)
\r
2463 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
\r
2464 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
\r
2465 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
\r
2466 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
\r
2467 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
\r
2468 #define CAN_BTR_SJW_Pos (24U)
\r
2469 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
\r
2470 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
\r
2471 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
\r
2472 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
\r
2473 #define CAN_BTR_LBKM_Pos (30U)
\r
2474 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
\r
2475 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
\r
2476 #define CAN_BTR_SILM_Pos (31U)
\r
2477 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
\r
2478 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
\r
2480 /*!<Mailbox registers */
\r
2481 /****************** Bit definition for CAN_TI0R register ********************/
\r
2482 #define CAN_TI0R_TXRQ_Pos (0U)
\r
2483 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
\r
2484 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
\r
2485 #define CAN_TI0R_RTR_Pos (1U)
\r
2486 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
\r
2487 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
\r
2488 #define CAN_TI0R_IDE_Pos (2U)
\r
2489 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
\r
2490 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
\r
2491 #define CAN_TI0R_EXID_Pos (3U)
\r
2492 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
\r
2493 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
\r
2494 #define CAN_TI0R_STID_Pos (21U)
\r
2495 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
\r
2496 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
\r
2498 /****************** Bit definition for CAN_TDT0R register *******************/
\r
2499 #define CAN_TDT0R_DLC_Pos (0U)
\r
2500 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
\r
2501 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
\r
2502 #define CAN_TDT0R_TGT_Pos (8U)
\r
2503 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
\r
2504 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
\r
2505 #define CAN_TDT0R_TIME_Pos (16U)
\r
2506 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
\r
2507 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
\r
2509 /****************** Bit definition for CAN_TDL0R register *******************/
\r
2510 #define CAN_TDL0R_DATA0_Pos (0U)
\r
2511 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
\r
2512 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
\r
2513 #define CAN_TDL0R_DATA1_Pos (8U)
\r
2514 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
\r
2515 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
\r
2516 #define CAN_TDL0R_DATA2_Pos (16U)
\r
2517 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
\r
2518 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
\r
2519 #define CAN_TDL0R_DATA3_Pos (24U)
\r
2520 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
\r
2521 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
\r
2523 /****************** Bit definition for CAN_TDH0R register *******************/
\r
2524 #define CAN_TDH0R_DATA4_Pos (0U)
\r
2525 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
\r
2526 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
\r
2527 #define CAN_TDH0R_DATA5_Pos (8U)
\r
2528 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
\r
2529 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
\r
2530 #define CAN_TDH0R_DATA6_Pos (16U)
\r
2531 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
\r
2532 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
\r
2533 #define CAN_TDH0R_DATA7_Pos (24U)
\r
2534 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
\r
2535 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
\r
2537 /******************* Bit definition for CAN_TI1R register *******************/
\r
2538 #define CAN_TI1R_TXRQ_Pos (0U)
\r
2539 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
\r
2540 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
\r
2541 #define CAN_TI1R_RTR_Pos (1U)
\r
2542 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
\r
2543 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
\r
2544 #define CAN_TI1R_IDE_Pos (2U)
\r
2545 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
\r
2546 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
\r
2547 #define CAN_TI1R_EXID_Pos (3U)
\r
2548 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
\r
2549 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
\r
2550 #define CAN_TI1R_STID_Pos (21U)
\r
2551 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
\r
2552 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
\r
2554 /******************* Bit definition for CAN_TDT1R register ******************/
\r
2555 #define CAN_TDT1R_DLC_Pos (0U)
\r
2556 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
\r
2557 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
\r
2558 #define CAN_TDT1R_TGT_Pos (8U)
\r
2559 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
\r
2560 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
\r
2561 #define CAN_TDT1R_TIME_Pos (16U)
\r
2562 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
\r
2563 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
\r
2565 /******************* Bit definition for CAN_TDL1R register ******************/
\r
2566 #define CAN_TDL1R_DATA0_Pos (0U)
\r
2567 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
\r
2568 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
\r
2569 #define CAN_TDL1R_DATA1_Pos (8U)
\r
2570 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
\r
2571 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
\r
2572 #define CAN_TDL1R_DATA2_Pos (16U)
\r
2573 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
\r
2574 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
\r
2575 #define CAN_TDL1R_DATA3_Pos (24U)
\r
2576 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
\r
2577 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
\r
2579 /******************* Bit definition for CAN_TDH1R register ******************/
\r
2580 #define CAN_TDH1R_DATA4_Pos (0U)
\r
2581 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
\r
2582 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
\r
2583 #define CAN_TDH1R_DATA5_Pos (8U)
\r
2584 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
\r
2585 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
\r
2586 #define CAN_TDH1R_DATA6_Pos (16U)
\r
2587 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
\r
2588 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
\r
2589 #define CAN_TDH1R_DATA7_Pos (24U)
\r
2590 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
\r
2591 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
\r
2593 /******************* Bit definition for CAN_TI2R register *******************/
\r
2594 #define CAN_TI2R_TXRQ_Pos (0U)
\r
2595 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
\r
2596 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
\r
2597 #define CAN_TI2R_RTR_Pos (1U)
\r
2598 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
\r
2599 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
\r
2600 #define CAN_TI2R_IDE_Pos (2U)
\r
2601 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
\r
2602 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
\r
2603 #define CAN_TI2R_EXID_Pos (3U)
\r
2604 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
\r
2605 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
\r
2606 #define CAN_TI2R_STID_Pos (21U)
\r
2607 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
\r
2608 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
\r
2610 /******************* Bit definition for CAN_TDT2R register ******************/
\r
2611 #define CAN_TDT2R_DLC_Pos (0U)
\r
2612 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
\r
2613 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
\r
2614 #define CAN_TDT2R_TGT_Pos (8U)
\r
2615 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
\r
2616 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
\r
2617 #define CAN_TDT2R_TIME_Pos (16U)
\r
2618 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
\r
2619 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
\r
2621 /******************* Bit definition for CAN_TDL2R register ******************/
\r
2622 #define CAN_TDL2R_DATA0_Pos (0U)
\r
2623 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
\r
2624 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
\r
2625 #define CAN_TDL2R_DATA1_Pos (8U)
\r
2626 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
\r
2627 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
\r
2628 #define CAN_TDL2R_DATA2_Pos (16U)
\r
2629 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
\r
2630 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
\r
2631 #define CAN_TDL2R_DATA3_Pos (24U)
\r
2632 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
\r
2633 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
\r
2635 /******************* Bit definition for CAN_TDH2R register ******************/
\r
2636 #define CAN_TDH2R_DATA4_Pos (0U)
\r
2637 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
\r
2638 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
\r
2639 #define CAN_TDH2R_DATA5_Pos (8U)
\r
2640 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
\r
2641 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
\r
2642 #define CAN_TDH2R_DATA6_Pos (16U)
\r
2643 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
\r
2644 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
\r
2645 #define CAN_TDH2R_DATA7_Pos (24U)
\r
2646 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
\r
2647 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
\r
2649 /******************* Bit definition for CAN_RI0R register *******************/
\r
2650 #define CAN_RI0R_RTR_Pos (1U)
\r
2651 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
\r
2652 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
\r
2653 #define CAN_RI0R_IDE_Pos (2U)
\r
2654 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
\r
2655 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
\r
2656 #define CAN_RI0R_EXID_Pos (3U)
\r
2657 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
\r
2658 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
\r
2659 #define CAN_RI0R_STID_Pos (21U)
\r
2660 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
\r
2661 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
\r
2663 /******************* Bit definition for CAN_RDT0R register ******************/
\r
2664 #define CAN_RDT0R_DLC_Pos (0U)
\r
2665 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
\r
2666 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
\r
2667 #define CAN_RDT0R_FMI_Pos (8U)
\r
2668 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
\r
2669 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
\r
2670 #define CAN_RDT0R_TIME_Pos (16U)
\r
2671 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
\r
2672 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
\r
2674 /******************* Bit definition for CAN_RDL0R register ******************/
\r
2675 #define CAN_RDL0R_DATA0_Pos (0U)
\r
2676 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
\r
2677 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
\r
2678 #define CAN_RDL0R_DATA1_Pos (8U)
\r
2679 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
\r
2680 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
\r
2681 #define CAN_RDL0R_DATA2_Pos (16U)
\r
2682 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
\r
2683 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
\r
2684 #define CAN_RDL0R_DATA3_Pos (24U)
\r
2685 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
\r
2686 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
\r
2688 /******************* Bit definition for CAN_RDH0R register ******************/
\r
2689 #define CAN_RDH0R_DATA4_Pos (0U)
\r
2690 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
\r
2691 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
\r
2692 #define CAN_RDH0R_DATA5_Pos (8U)
\r
2693 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
\r
2694 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
\r
2695 #define CAN_RDH0R_DATA6_Pos (16U)
\r
2696 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
\r
2697 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
\r
2698 #define CAN_RDH0R_DATA7_Pos (24U)
\r
2699 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
\r
2700 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
\r
2702 /******************* Bit definition for CAN_RI1R register *******************/
\r
2703 #define CAN_RI1R_RTR_Pos (1U)
\r
2704 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
\r
2705 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
\r
2706 #define CAN_RI1R_IDE_Pos (2U)
\r
2707 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
\r
2708 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
\r
2709 #define CAN_RI1R_EXID_Pos (3U)
\r
2710 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
\r
2711 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
\r
2712 #define CAN_RI1R_STID_Pos (21U)
\r
2713 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
\r
2714 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
\r
2716 /******************* Bit definition for CAN_RDT1R register ******************/
\r
2717 #define CAN_RDT1R_DLC_Pos (0U)
\r
2718 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
\r
2719 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
\r
2720 #define CAN_RDT1R_FMI_Pos (8U)
\r
2721 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
\r
2722 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
\r
2723 #define CAN_RDT1R_TIME_Pos (16U)
\r
2724 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
\r
2725 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
\r
2727 /******************* Bit definition for CAN_RDL1R register ******************/
\r
2728 #define CAN_RDL1R_DATA0_Pos (0U)
\r
2729 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
\r
2730 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
\r
2731 #define CAN_RDL1R_DATA1_Pos (8U)
\r
2732 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
\r
2733 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
\r
2734 #define CAN_RDL1R_DATA2_Pos (16U)
\r
2735 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
\r
2736 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
\r
2737 #define CAN_RDL1R_DATA3_Pos (24U)
\r
2738 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
\r
2739 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
\r
2741 /******************* Bit definition for CAN_RDH1R register ******************/
\r
2742 #define CAN_RDH1R_DATA4_Pos (0U)
\r
2743 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
\r
2744 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
\r
2745 #define CAN_RDH1R_DATA5_Pos (8U)
\r
2746 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
\r
2747 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
\r
2748 #define CAN_RDH1R_DATA6_Pos (16U)
\r
2749 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
\r
2750 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
\r
2751 #define CAN_RDH1R_DATA7_Pos (24U)
\r
2752 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
\r
2753 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
\r
2755 /*!<CAN filter registers */
\r
2756 /******************* Bit definition for CAN_FMR register ********************/
\r
2757 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
\r
2758 #define CAN_FMR_CAN2SB_Pos (8U)
\r
2759 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
\r
2760 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
\r
2762 /******************* Bit definition for CAN_FM1R register *******************/
\r
2763 #define CAN_FM1R_FBM_Pos (0U)
\r
2764 #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
\r
2765 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
\r
2766 #define CAN_FM1R_FBM0_Pos (0U)
\r
2767 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
\r
2768 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
\r
2769 #define CAN_FM1R_FBM1_Pos (1U)
\r
2770 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
\r
2771 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
\r
2772 #define CAN_FM1R_FBM2_Pos (2U)
\r
2773 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
\r
2774 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
\r
2775 #define CAN_FM1R_FBM3_Pos (3U)
\r
2776 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
\r
2777 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
\r
2778 #define CAN_FM1R_FBM4_Pos (4U)
\r
2779 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
\r
2780 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
\r
2781 #define CAN_FM1R_FBM5_Pos (5U)
\r
2782 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
\r
2783 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
\r
2784 #define CAN_FM1R_FBM6_Pos (6U)
\r
2785 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
\r
2786 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
\r
2787 #define CAN_FM1R_FBM7_Pos (7U)
\r
2788 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
\r
2789 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
\r
2790 #define CAN_FM1R_FBM8_Pos (8U)
\r
2791 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
\r
2792 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
\r
2793 #define CAN_FM1R_FBM9_Pos (9U)
\r
2794 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
\r
2795 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
\r
2796 #define CAN_FM1R_FBM10_Pos (10U)
\r
2797 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
\r
2798 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
\r
2799 #define CAN_FM1R_FBM11_Pos (11U)
\r
2800 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
\r
2801 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
\r
2802 #define CAN_FM1R_FBM12_Pos (12U)
\r
2803 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
\r
2804 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
\r
2805 #define CAN_FM1R_FBM13_Pos (13U)
\r
2806 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
\r
2807 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
\r
2809 /******************* Bit definition for CAN_FS1R register *******************/
\r
2810 #define CAN_FS1R_FSC_Pos (0U)
\r
2811 #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
\r
2812 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
\r
2813 #define CAN_FS1R_FSC0_Pos (0U)
\r
2814 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
\r
2815 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
\r
2816 #define CAN_FS1R_FSC1_Pos (1U)
\r
2817 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
\r
2818 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
\r
2819 #define CAN_FS1R_FSC2_Pos (2U)
\r
2820 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
\r
2821 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
\r
2822 #define CAN_FS1R_FSC3_Pos (3U)
\r
2823 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
\r
2824 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
\r
2825 #define CAN_FS1R_FSC4_Pos (4U)
\r
2826 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
\r
2827 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
\r
2828 #define CAN_FS1R_FSC5_Pos (5U)
\r
2829 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
\r
2830 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
\r
2831 #define CAN_FS1R_FSC6_Pos (6U)
\r
2832 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
\r
2833 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
\r
2834 #define CAN_FS1R_FSC7_Pos (7U)
\r
2835 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
\r
2836 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
\r
2837 #define CAN_FS1R_FSC8_Pos (8U)
\r
2838 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
\r
2839 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
\r
2840 #define CAN_FS1R_FSC9_Pos (9U)
\r
2841 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
\r
2842 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
\r
2843 #define CAN_FS1R_FSC10_Pos (10U)
\r
2844 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
\r
2845 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
\r
2846 #define CAN_FS1R_FSC11_Pos (11U)
\r
2847 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
\r
2848 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
\r
2849 #define CAN_FS1R_FSC12_Pos (12U)
\r
2850 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
\r
2851 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
\r
2852 #define CAN_FS1R_FSC13_Pos (13U)
\r
2853 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
\r
2854 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
\r
2856 /****************** Bit definition for CAN_FFA1R register *******************/
\r
2857 #define CAN_FFA1R_FFA_Pos (0U)
\r
2858 #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
\r
2859 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
\r
2860 #define CAN_FFA1R_FFA0_Pos (0U)
\r
2861 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
\r
2862 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
\r
2863 #define CAN_FFA1R_FFA1_Pos (1U)
\r
2864 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
\r
2865 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
\r
2866 #define CAN_FFA1R_FFA2_Pos (2U)
\r
2867 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
\r
2868 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
\r
2869 #define CAN_FFA1R_FFA3_Pos (3U)
\r
2870 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
\r
2871 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
\r
2872 #define CAN_FFA1R_FFA4_Pos (4U)
\r
2873 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
\r
2874 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
\r
2875 #define CAN_FFA1R_FFA5_Pos (5U)
\r
2876 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
\r
2877 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
\r
2878 #define CAN_FFA1R_FFA6_Pos (6U)
\r
2879 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
\r
2880 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
\r
2881 #define CAN_FFA1R_FFA7_Pos (7U)
\r
2882 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
\r
2883 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
\r
2884 #define CAN_FFA1R_FFA8_Pos (8U)
\r
2885 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
\r
2886 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
\r
2887 #define CAN_FFA1R_FFA9_Pos (9U)
\r
2888 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
\r
2889 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
\r
2890 #define CAN_FFA1R_FFA10_Pos (10U)
\r
2891 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
\r
2892 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
\r
2893 #define CAN_FFA1R_FFA11_Pos (11U)
\r
2894 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
\r
2895 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
\r
2896 #define CAN_FFA1R_FFA12_Pos (12U)
\r
2897 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
\r
2898 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
\r
2899 #define CAN_FFA1R_FFA13_Pos (13U)
\r
2900 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
\r
2901 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
\r
2903 /******************* Bit definition for CAN_FA1R register *******************/
\r
2904 #define CAN_FA1R_FACT_Pos (0U)
\r
2905 #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
\r
2906 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
\r
2907 #define CAN_FA1R_FACT0_Pos (0U)
\r
2908 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
\r
2909 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
\r
2910 #define CAN_FA1R_FACT1_Pos (1U)
\r
2911 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
\r
2912 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
\r
2913 #define CAN_FA1R_FACT2_Pos (2U)
\r
2914 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
\r
2915 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
\r
2916 #define CAN_FA1R_FACT3_Pos (3U)
\r
2917 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
\r
2918 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
\r
2919 #define CAN_FA1R_FACT4_Pos (4U)
\r
2920 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
\r
2921 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
\r
2922 #define CAN_FA1R_FACT5_Pos (5U)
\r
2923 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
\r
2924 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
\r
2925 #define CAN_FA1R_FACT6_Pos (6U)
\r
2926 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
\r
2927 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
\r
2928 #define CAN_FA1R_FACT7_Pos (7U)
\r
2929 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
\r
2930 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
\r
2931 #define CAN_FA1R_FACT8_Pos (8U)
\r
2932 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
\r
2933 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
\r
2934 #define CAN_FA1R_FACT9_Pos (9U)
\r
2935 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
\r
2936 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
\r
2937 #define CAN_FA1R_FACT10_Pos (10U)
\r
2938 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
\r
2939 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
\r
2940 #define CAN_FA1R_FACT11_Pos (11U)
\r
2941 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
\r
2942 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
\r
2943 #define CAN_FA1R_FACT12_Pos (12U)
\r
2944 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
\r
2945 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
\r
2946 #define CAN_FA1R_FACT13_Pos (13U)
\r
2947 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
\r
2948 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
\r
2950 /******************* Bit definition for CAN_F0R1 register *******************/
\r
2951 #define CAN_F0R1_FB0_Pos (0U)
\r
2952 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
\r
2953 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
\r
2954 #define CAN_F0R1_FB1_Pos (1U)
\r
2955 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
\r
2956 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
\r
2957 #define CAN_F0R1_FB2_Pos (2U)
\r
2958 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
\r
2959 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
\r
2960 #define CAN_F0R1_FB3_Pos (3U)
\r
2961 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
\r
2962 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
\r
2963 #define CAN_F0R1_FB4_Pos (4U)
\r
2964 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
\r
2965 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
\r
2966 #define CAN_F0R1_FB5_Pos (5U)
\r
2967 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
\r
2968 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
\r
2969 #define CAN_F0R1_FB6_Pos (6U)
\r
2970 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
\r
2971 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
\r
2972 #define CAN_F0R1_FB7_Pos (7U)
\r
2973 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
\r
2974 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
\r
2975 #define CAN_F0R1_FB8_Pos (8U)
\r
2976 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
\r
2977 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
\r
2978 #define CAN_F0R1_FB9_Pos (9U)
\r
2979 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
\r
2980 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
\r
2981 #define CAN_F0R1_FB10_Pos (10U)
\r
2982 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
\r
2983 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
\r
2984 #define CAN_F0R1_FB11_Pos (11U)
\r
2985 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
\r
2986 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
\r
2987 #define CAN_F0R1_FB12_Pos (12U)
\r
2988 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
\r
2989 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
\r
2990 #define CAN_F0R1_FB13_Pos (13U)
\r
2991 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
\r
2992 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
\r
2993 #define CAN_F0R1_FB14_Pos (14U)
\r
2994 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
\r
2995 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
\r
2996 #define CAN_F0R1_FB15_Pos (15U)
\r
2997 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
\r
2998 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
\r
2999 #define CAN_F0R1_FB16_Pos (16U)
\r
3000 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
\r
3001 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
\r
3002 #define CAN_F0R1_FB17_Pos (17U)
\r
3003 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
\r
3004 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
\r
3005 #define CAN_F0R1_FB18_Pos (18U)
\r
3006 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
\r
3007 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
\r
3008 #define CAN_F0R1_FB19_Pos (19U)
\r
3009 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
\r
3010 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
\r
3011 #define CAN_F0R1_FB20_Pos (20U)
\r
3012 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
\r
3013 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
\r
3014 #define CAN_F0R1_FB21_Pos (21U)
\r
3015 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
\r
3016 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
\r
3017 #define CAN_F0R1_FB22_Pos (22U)
\r
3018 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
\r
3019 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
\r
3020 #define CAN_F0R1_FB23_Pos (23U)
\r
3021 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
\r
3022 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
\r
3023 #define CAN_F0R1_FB24_Pos (24U)
\r
3024 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
\r
3025 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
\r
3026 #define CAN_F0R1_FB25_Pos (25U)
\r
3027 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
\r
3028 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
\r
3029 #define CAN_F0R1_FB26_Pos (26U)
\r
3030 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
\r
3031 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
\r
3032 #define CAN_F0R1_FB27_Pos (27U)
\r
3033 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
\r
3034 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
\r
3035 #define CAN_F0R1_FB28_Pos (28U)
\r
3036 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
\r
3037 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
\r
3038 #define CAN_F0R1_FB29_Pos (29U)
\r
3039 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
\r
3040 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
\r
3041 #define CAN_F0R1_FB30_Pos (30U)
\r
3042 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
\r
3043 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
\r
3044 #define CAN_F0R1_FB31_Pos (31U)
\r
3045 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
\r
3046 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
\r
3048 /******************* Bit definition for CAN_F1R1 register *******************/
\r
3049 #define CAN_F1R1_FB0_Pos (0U)
\r
3050 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
\r
3051 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
\r
3052 #define CAN_F1R1_FB1_Pos (1U)
\r
3053 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
\r
3054 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
\r
3055 #define CAN_F1R1_FB2_Pos (2U)
\r
3056 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
\r
3057 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
\r
3058 #define CAN_F1R1_FB3_Pos (3U)
\r
3059 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
\r
3060 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
\r
3061 #define CAN_F1R1_FB4_Pos (4U)
\r
3062 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
\r
3063 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
\r
3064 #define CAN_F1R1_FB5_Pos (5U)
\r
3065 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
\r
3066 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
\r
3067 #define CAN_F1R1_FB6_Pos (6U)
\r
3068 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
\r
3069 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
\r
3070 #define CAN_F1R1_FB7_Pos (7U)
\r
3071 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
\r
3072 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
\r
3073 #define CAN_F1R1_FB8_Pos (8U)
\r
3074 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
\r
3075 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
\r
3076 #define CAN_F1R1_FB9_Pos (9U)
\r
3077 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
\r
3078 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
\r
3079 #define CAN_F1R1_FB10_Pos (10U)
\r
3080 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
\r
3081 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
\r
3082 #define CAN_F1R1_FB11_Pos (11U)
\r
3083 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
\r
3084 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
\r
3085 #define CAN_F1R1_FB12_Pos (12U)
\r
3086 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
\r
3087 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
\r
3088 #define CAN_F1R1_FB13_Pos (13U)
\r
3089 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
\r
3090 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
\r
3091 #define CAN_F1R1_FB14_Pos (14U)
\r
3092 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
\r
3093 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
\r
3094 #define CAN_F1R1_FB15_Pos (15U)
\r
3095 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
\r
3096 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
\r
3097 #define CAN_F1R1_FB16_Pos (16U)
\r
3098 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
\r
3099 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
\r
3100 #define CAN_F1R1_FB17_Pos (17U)
\r
3101 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
\r
3102 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
\r
3103 #define CAN_F1R1_FB18_Pos (18U)
\r
3104 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
\r
3105 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
\r
3106 #define CAN_F1R1_FB19_Pos (19U)
\r
3107 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
\r
3108 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
\r
3109 #define CAN_F1R1_FB20_Pos (20U)
\r
3110 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
\r
3111 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
\r
3112 #define CAN_F1R1_FB21_Pos (21U)
\r
3113 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
\r
3114 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
\r
3115 #define CAN_F1R1_FB22_Pos (22U)
\r
3116 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
\r
3117 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
\r
3118 #define CAN_F1R1_FB23_Pos (23U)
\r
3119 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
\r
3120 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
\r
3121 #define CAN_F1R1_FB24_Pos (24U)
\r
3122 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
\r
3123 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
\r
3124 #define CAN_F1R1_FB25_Pos (25U)
\r
3125 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
\r
3126 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
\r
3127 #define CAN_F1R1_FB26_Pos (26U)
\r
3128 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
\r
3129 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
\r
3130 #define CAN_F1R1_FB27_Pos (27U)
\r
3131 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
\r
3132 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
\r
3133 #define CAN_F1R1_FB28_Pos (28U)
\r
3134 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
\r
3135 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
\r
3136 #define CAN_F1R1_FB29_Pos (29U)
\r
3137 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
\r
3138 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
\r
3139 #define CAN_F1R1_FB30_Pos (30U)
\r
3140 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
\r
3141 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
\r
3142 #define CAN_F1R1_FB31_Pos (31U)
\r
3143 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
\r
3144 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
\r
3146 /******************* Bit definition for CAN_F2R1 register *******************/
\r
3147 #define CAN_F2R1_FB0_Pos (0U)
\r
3148 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
\r
3149 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
\r
3150 #define CAN_F2R1_FB1_Pos (1U)
\r
3151 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
\r
3152 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
\r
3153 #define CAN_F2R1_FB2_Pos (2U)
\r
3154 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
\r
3155 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
\r
3156 #define CAN_F2R1_FB3_Pos (3U)
\r
3157 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
\r
3158 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
\r
3159 #define CAN_F2R1_FB4_Pos (4U)
\r
3160 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
\r
3161 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
\r
3162 #define CAN_F2R1_FB5_Pos (5U)
\r
3163 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
\r
3164 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
\r
3165 #define CAN_F2R1_FB6_Pos (6U)
\r
3166 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
\r
3167 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
\r
3168 #define CAN_F2R1_FB7_Pos (7U)
\r
3169 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
\r
3170 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
\r
3171 #define CAN_F2R1_FB8_Pos (8U)
\r
3172 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
\r
3173 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
\r
3174 #define CAN_F2R1_FB9_Pos (9U)
\r
3175 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
\r
3176 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
\r
3177 #define CAN_F2R1_FB10_Pos (10U)
\r
3178 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
\r
3179 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
\r
3180 #define CAN_F2R1_FB11_Pos (11U)
\r
3181 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
\r
3182 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
\r
3183 #define CAN_F2R1_FB12_Pos (12U)
\r
3184 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
\r
3185 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
\r
3186 #define CAN_F2R1_FB13_Pos (13U)
\r
3187 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
\r
3188 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
\r
3189 #define CAN_F2R1_FB14_Pos (14U)
\r
3190 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
\r
3191 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
\r
3192 #define CAN_F2R1_FB15_Pos (15U)
\r
3193 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
\r
3194 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
\r
3195 #define CAN_F2R1_FB16_Pos (16U)
\r
3196 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
\r
3197 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
\r
3198 #define CAN_F2R1_FB17_Pos (17U)
\r
3199 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
\r
3200 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
\r
3201 #define CAN_F2R1_FB18_Pos (18U)
\r
3202 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
\r
3203 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
\r
3204 #define CAN_F2R1_FB19_Pos (19U)
\r
3205 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
\r
3206 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
\r
3207 #define CAN_F2R1_FB20_Pos (20U)
\r
3208 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
\r
3209 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
\r
3210 #define CAN_F2R1_FB21_Pos (21U)
\r
3211 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
\r
3212 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
\r
3213 #define CAN_F2R1_FB22_Pos (22U)
\r
3214 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
\r
3215 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
\r
3216 #define CAN_F2R1_FB23_Pos (23U)
\r
3217 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
\r
3218 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
\r
3219 #define CAN_F2R1_FB24_Pos (24U)
\r
3220 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
\r
3221 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
\r
3222 #define CAN_F2R1_FB25_Pos (25U)
\r
3223 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
\r
3224 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
\r
3225 #define CAN_F2R1_FB26_Pos (26U)
\r
3226 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
\r
3227 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
\r
3228 #define CAN_F2R1_FB27_Pos (27U)
\r
3229 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
\r
3230 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
\r
3231 #define CAN_F2R1_FB28_Pos (28U)
\r
3232 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
\r
3233 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
\r
3234 #define CAN_F2R1_FB29_Pos (29U)
\r
3235 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
\r
3236 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
\r
3237 #define CAN_F2R1_FB30_Pos (30U)
\r
3238 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
\r
3239 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
\r
3240 #define CAN_F2R1_FB31_Pos (31U)
\r
3241 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
\r
3242 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
\r
3244 /******************* Bit definition for CAN_F3R1 register *******************/
\r
3245 #define CAN_F3R1_FB0_Pos (0U)
\r
3246 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
\r
3247 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
\r
3248 #define CAN_F3R1_FB1_Pos (1U)
\r
3249 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
\r
3250 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
\r
3251 #define CAN_F3R1_FB2_Pos (2U)
\r
3252 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
\r
3253 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
\r
3254 #define CAN_F3R1_FB3_Pos (3U)
\r
3255 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
\r
3256 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
\r
3257 #define CAN_F3R1_FB4_Pos (4U)
\r
3258 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
\r
3259 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
\r
3260 #define CAN_F3R1_FB5_Pos (5U)
\r
3261 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
\r
3262 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
\r
3263 #define CAN_F3R1_FB6_Pos (6U)
\r
3264 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
\r
3265 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
\r
3266 #define CAN_F3R1_FB7_Pos (7U)
\r
3267 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
\r
3268 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
\r
3269 #define CAN_F3R1_FB8_Pos (8U)
\r
3270 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
\r
3271 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
\r
3272 #define CAN_F3R1_FB9_Pos (9U)
\r
3273 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
\r
3274 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
\r
3275 #define CAN_F3R1_FB10_Pos (10U)
\r
3276 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
\r
3277 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
\r
3278 #define CAN_F3R1_FB11_Pos (11U)
\r
3279 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
\r
3280 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
\r
3281 #define CAN_F3R1_FB12_Pos (12U)
\r
3282 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
\r
3283 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
\r
3284 #define CAN_F3R1_FB13_Pos (13U)
\r
3285 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
\r
3286 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
\r
3287 #define CAN_F3R1_FB14_Pos (14U)
\r
3288 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
\r
3289 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
\r
3290 #define CAN_F3R1_FB15_Pos (15U)
\r
3291 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
\r
3292 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
\r
3293 #define CAN_F3R1_FB16_Pos (16U)
\r
3294 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
\r
3295 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
\r
3296 #define CAN_F3R1_FB17_Pos (17U)
\r
3297 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
\r
3298 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
\r
3299 #define CAN_F3R1_FB18_Pos (18U)
\r
3300 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
\r
3301 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
\r
3302 #define CAN_F3R1_FB19_Pos (19U)
\r
3303 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
\r
3304 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
\r
3305 #define CAN_F3R1_FB20_Pos (20U)
\r
3306 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
\r
3307 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
\r
3308 #define CAN_F3R1_FB21_Pos (21U)
\r
3309 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
\r
3310 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
\r
3311 #define CAN_F3R1_FB22_Pos (22U)
\r
3312 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
\r
3313 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
\r
3314 #define CAN_F3R1_FB23_Pos (23U)
\r
3315 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
\r
3316 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
\r
3317 #define CAN_F3R1_FB24_Pos (24U)
\r
3318 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
\r
3319 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
\r
3320 #define CAN_F3R1_FB25_Pos (25U)
\r
3321 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
\r
3322 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
\r
3323 #define CAN_F3R1_FB26_Pos (26U)
\r
3324 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
\r
3325 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
\r
3326 #define CAN_F3R1_FB27_Pos (27U)
\r
3327 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
\r
3328 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
\r
3329 #define CAN_F3R1_FB28_Pos (28U)
\r
3330 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
\r
3331 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
\r
3332 #define CAN_F3R1_FB29_Pos (29U)
\r
3333 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
\r
3334 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
\r
3335 #define CAN_F3R1_FB30_Pos (30U)
\r
3336 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
\r
3337 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
\r
3338 #define CAN_F3R1_FB31_Pos (31U)
\r
3339 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
\r
3340 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
\r
3342 /******************* Bit definition for CAN_F4R1 register *******************/
\r
3343 #define CAN_F4R1_FB0_Pos (0U)
\r
3344 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
\r
3345 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
\r
3346 #define CAN_F4R1_FB1_Pos (1U)
\r
3347 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
\r
3348 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
\r
3349 #define CAN_F4R1_FB2_Pos (2U)
\r
3350 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
\r
3351 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
\r
3352 #define CAN_F4R1_FB3_Pos (3U)
\r
3353 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
\r
3354 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
\r
3355 #define CAN_F4R1_FB4_Pos (4U)
\r
3356 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
\r
3357 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
\r
3358 #define CAN_F4R1_FB5_Pos (5U)
\r
3359 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
\r
3360 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
\r
3361 #define CAN_F4R1_FB6_Pos (6U)
\r
3362 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
\r
3363 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
\r
3364 #define CAN_F4R1_FB7_Pos (7U)
\r
3365 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
\r
3366 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
\r
3367 #define CAN_F4R1_FB8_Pos (8U)
\r
3368 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
\r
3369 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
\r
3370 #define CAN_F4R1_FB9_Pos (9U)
\r
3371 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
\r
3372 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
\r
3373 #define CAN_F4R1_FB10_Pos (10U)
\r
3374 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
\r
3375 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
\r
3376 #define CAN_F4R1_FB11_Pos (11U)
\r
3377 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
\r
3378 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
\r
3379 #define CAN_F4R1_FB12_Pos (12U)
\r
3380 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
\r
3381 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
\r
3382 #define CAN_F4R1_FB13_Pos (13U)
\r
3383 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
\r
3384 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
\r
3385 #define CAN_F4R1_FB14_Pos (14U)
\r
3386 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
\r
3387 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
\r
3388 #define CAN_F4R1_FB15_Pos (15U)
\r
3389 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
\r
3390 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
\r
3391 #define CAN_F4R1_FB16_Pos (16U)
\r
3392 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
\r
3393 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
\r
3394 #define CAN_F4R1_FB17_Pos (17U)
\r
3395 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
\r
3396 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
\r
3397 #define CAN_F4R1_FB18_Pos (18U)
\r
3398 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
\r
3399 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
\r
3400 #define CAN_F4R1_FB19_Pos (19U)
\r
3401 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
\r
3402 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
\r
3403 #define CAN_F4R1_FB20_Pos (20U)
\r
3404 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
\r
3405 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
\r
3406 #define CAN_F4R1_FB21_Pos (21U)
\r
3407 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
\r
3408 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
\r
3409 #define CAN_F4R1_FB22_Pos (22U)
\r
3410 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
\r
3411 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
\r
3412 #define CAN_F4R1_FB23_Pos (23U)
\r
3413 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
\r
3414 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
\r
3415 #define CAN_F4R1_FB24_Pos (24U)
\r
3416 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
\r
3417 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
\r
3418 #define CAN_F4R1_FB25_Pos (25U)
\r
3419 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
\r
3420 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
\r
3421 #define CAN_F4R1_FB26_Pos (26U)
\r
3422 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
\r
3423 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
\r
3424 #define CAN_F4R1_FB27_Pos (27U)
\r
3425 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
\r
3426 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
\r
3427 #define CAN_F4R1_FB28_Pos (28U)
\r
3428 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
\r
3429 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
\r
3430 #define CAN_F4R1_FB29_Pos (29U)
\r
3431 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
\r
3432 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
\r
3433 #define CAN_F4R1_FB30_Pos (30U)
\r
3434 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
\r
3435 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
\r
3436 #define CAN_F4R1_FB31_Pos (31U)
\r
3437 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
\r
3438 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
\r
3440 /******************* Bit definition for CAN_F5R1 register *******************/
\r
3441 #define CAN_F5R1_FB0_Pos (0U)
\r
3442 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
\r
3443 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
\r
3444 #define CAN_F5R1_FB1_Pos (1U)
\r
3445 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
\r
3446 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
\r
3447 #define CAN_F5R1_FB2_Pos (2U)
\r
3448 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
\r
3449 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
\r
3450 #define CAN_F5R1_FB3_Pos (3U)
\r
3451 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
\r
3452 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
\r
3453 #define CAN_F5R1_FB4_Pos (4U)
\r
3454 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
\r
3455 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
\r
3456 #define CAN_F5R1_FB5_Pos (5U)
\r
3457 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
\r
3458 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
\r
3459 #define CAN_F5R1_FB6_Pos (6U)
\r
3460 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
\r
3461 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
\r
3462 #define CAN_F5R1_FB7_Pos (7U)
\r
3463 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
\r
3464 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
\r
3465 #define CAN_F5R1_FB8_Pos (8U)
\r
3466 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
\r
3467 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
\r
3468 #define CAN_F5R1_FB9_Pos (9U)
\r
3469 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
\r
3470 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
\r
3471 #define CAN_F5R1_FB10_Pos (10U)
\r
3472 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
\r
3473 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
\r
3474 #define CAN_F5R1_FB11_Pos (11U)
\r
3475 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
\r
3476 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
\r
3477 #define CAN_F5R1_FB12_Pos (12U)
\r
3478 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
\r
3479 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
\r
3480 #define CAN_F5R1_FB13_Pos (13U)
\r
3481 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
\r
3482 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
\r
3483 #define CAN_F5R1_FB14_Pos (14U)
\r
3484 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
\r
3485 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
\r
3486 #define CAN_F5R1_FB15_Pos (15U)
\r
3487 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
\r
3488 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
\r
3489 #define CAN_F5R1_FB16_Pos (16U)
\r
3490 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
\r
3491 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
\r
3492 #define CAN_F5R1_FB17_Pos (17U)
\r
3493 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
\r
3494 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
\r
3495 #define CAN_F5R1_FB18_Pos (18U)
\r
3496 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
\r
3497 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
\r
3498 #define CAN_F5R1_FB19_Pos (19U)
\r
3499 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
\r
3500 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
\r
3501 #define CAN_F5R1_FB20_Pos (20U)
\r
3502 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
\r
3503 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
\r
3504 #define CAN_F5R1_FB21_Pos (21U)
\r
3505 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
\r
3506 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
\r
3507 #define CAN_F5R1_FB22_Pos (22U)
\r
3508 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
\r
3509 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
\r
3510 #define CAN_F5R1_FB23_Pos (23U)
\r
3511 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
\r
3512 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
\r
3513 #define CAN_F5R1_FB24_Pos (24U)
\r
3514 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
\r
3515 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
\r
3516 #define CAN_F5R1_FB25_Pos (25U)
\r
3517 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
\r
3518 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
\r
3519 #define CAN_F5R1_FB26_Pos (26U)
\r
3520 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
\r
3521 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
\r
3522 #define CAN_F5R1_FB27_Pos (27U)
\r
3523 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
\r
3524 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
\r
3525 #define CAN_F5R1_FB28_Pos (28U)
\r
3526 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
\r
3527 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
\r
3528 #define CAN_F5R1_FB29_Pos (29U)
\r
3529 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
\r
3530 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
\r
3531 #define CAN_F5R1_FB30_Pos (30U)
\r
3532 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
\r
3533 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
\r
3534 #define CAN_F5R1_FB31_Pos (31U)
\r
3535 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
\r
3536 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
\r
3538 /******************* Bit definition for CAN_F6R1 register *******************/
\r
3539 #define CAN_F6R1_FB0_Pos (0U)
\r
3540 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
\r
3541 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
\r
3542 #define CAN_F6R1_FB1_Pos (1U)
\r
3543 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
\r
3544 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
\r
3545 #define CAN_F6R1_FB2_Pos (2U)
\r
3546 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
\r
3547 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
\r
3548 #define CAN_F6R1_FB3_Pos (3U)
\r
3549 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
\r
3550 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
\r
3551 #define CAN_F6R1_FB4_Pos (4U)
\r
3552 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
\r
3553 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
\r
3554 #define CAN_F6R1_FB5_Pos (5U)
\r
3555 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
\r
3556 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
\r
3557 #define CAN_F6R1_FB6_Pos (6U)
\r
3558 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
\r
3559 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
\r
3560 #define CAN_F6R1_FB7_Pos (7U)
\r
3561 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
\r
3562 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
\r
3563 #define CAN_F6R1_FB8_Pos (8U)
\r
3564 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
\r
3565 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
\r
3566 #define CAN_F6R1_FB9_Pos (9U)
\r
3567 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
\r
3568 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
\r
3569 #define CAN_F6R1_FB10_Pos (10U)
\r
3570 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
\r
3571 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
\r
3572 #define CAN_F6R1_FB11_Pos (11U)
\r
3573 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
\r
3574 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
\r
3575 #define CAN_F6R1_FB12_Pos (12U)
\r
3576 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
\r
3577 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
\r
3578 #define CAN_F6R1_FB13_Pos (13U)
\r
3579 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
\r
3580 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
\r
3581 #define CAN_F6R1_FB14_Pos (14U)
\r
3582 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
\r
3583 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
\r
3584 #define CAN_F6R1_FB15_Pos (15U)
\r
3585 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
\r
3586 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
\r
3587 #define CAN_F6R1_FB16_Pos (16U)
\r
3588 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
\r
3589 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
\r
3590 #define CAN_F6R1_FB17_Pos (17U)
\r
3591 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
\r
3592 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
\r
3593 #define CAN_F6R1_FB18_Pos (18U)
\r
3594 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
\r
3595 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
\r
3596 #define CAN_F6R1_FB19_Pos (19U)
\r
3597 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
\r
3598 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
\r
3599 #define CAN_F6R1_FB20_Pos (20U)
\r
3600 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
\r
3601 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
\r
3602 #define CAN_F6R1_FB21_Pos (21U)
\r
3603 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
\r
3604 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
\r
3605 #define CAN_F6R1_FB22_Pos (22U)
\r
3606 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
\r
3607 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
\r
3608 #define CAN_F6R1_FB23_Pos (23U)
\r
3609 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
\r
3610 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
\r
3611 #define CAN_F6R1_FB24_Pos (24U)
\r
3612 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
\r
3613 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
\r
3614 #define CAN_F6R1_FB25_Pos (25U)
\r
3615 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
\r
3616 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
\r
3617 #define CAN_F6R1_FB26_Pos (26U)
\r
3618 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
\r
3619 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
\r
3620 #define CAN_F6R1_FB27_Pos (27U)
\r
3621 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
\r
3622 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
\r
3623 #define CAN_F6R1_FB28_Pos (28U)
\r
3624 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
\r
3625 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
\r
3626 #define CAN_F6R1_FB29_Pos (29U)
\r
3627 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
\r
3628 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
\r
3629 #define CAN_F6R1_FB30_Pos (30U)
\r
3630 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
\r
3631 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
\r
3632 #define CAN_F6R1_FB31_Pos (31U)
\r
3633 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
\r
3634 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
\r
3636 /******************* Bit definition for CAN_F7R1 register *******************/
\r
3637 #define CAN_F7R1_FB0_Pos (0U)
\r
3638 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
\r
3639 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
\r
3640 #define CAN_F7R1_FB1_Pos (1U)
\r
3641 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
\r
3642 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
\r
3643 #define CAN_F7R1_FB2_Pos (2U)
\r
3644 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
\r
3645 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
\r
3646 #define CAN_F7R1_FB3_Pos (3U)
\r
3647 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
\r
3648 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
\r
3649 #define CAN_F7R1_FB4_Pos (4U)
\r
3650 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
\r
3651 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
\r
3652 #define CAN_F7R1_FB5_Pos (5U)
\r
3653 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
\r
3654 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
\r
3655 #define CAN_F7R1_FB6_Pos (6U)
\r
3656 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
\r
3657 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
\r
3658 #define CAN_F7R1_FB7_Pos (7U)
\r
3659 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
\r
3660 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
\r
3661 #define CAN_F7R1_FB8_Pos (8U)
\r
3662 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
\r
3663 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
\r
3664 #define CAN_F7R1_FB9_Pos (9U)
\r
3665 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
\r
3666 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
\r
3667 #define CAN_F7R1_FB10_Pos (10U)
\r
3668 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
\r
3669 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
\r
3670 #define CAN_F7R1_FB11_Pos (11U)
\r
3671 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
\r
3672 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
\r
3673 #define CAN_F7R1_FB12_Pos (12U)
\r
3674 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
\r
3675 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
\r
3676 #define CAN_F7R1_FB13_Pos (13U)
\r
3677 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
\r
3678 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
\r
3679 #define CAN_F7R1_FB14_Pos (14U)
\r
3680 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
\r
3681 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
\r
3682 #define CAN_F7R1_FB15_Pos (15U)
\r
3683 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
\r
3684 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
\r
3685 #define CAN_F7R1_FB16_Pos (16U)
\r
3686 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
\r
3687 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
\r
3688 #define CAN_F7R1_FB17_Pos (17U)
\r
3689 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
\r
3690 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
\r
3691 #define CAN_F7R1_FB18_Pos (18U)
\r
3692 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
\r
3693 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
\r
3694 #define CAN_F7R1_FB19_Pos (19U)
\r
3695 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
\r
3696 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
\r
3697 #define CAN_F7R1_FB20_Pos (20U)
\r
3698 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
\r
3699 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
\r
3700 #define CAN_F7R1_FB21_Pos (21U)
\r
3701 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
\r
3702 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
\r
3703 #define CAN_F7R1_FB22_Pos (22U)
\r
3704 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
\r
3705 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
\r
3706 #define CAN_F7R1_FB23_Pos (23U)
\r
3707 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
\r
3708 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
\r
3709 #define CAN_F7R1_FB24_Pos (24U)
\r
3710 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
\r
3711 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
\r
3712 #define CAN_F7R1_FB25_Pos (25U)
\r
3713 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
\r
3714 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
\r
3715 #define CAN_F7R1_FB26_Pos (26U)
\r
3716 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
\r
3717 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
\r
3718 #define CAN_F7R1_FB27_Pos (27U)
\r
3719 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
\r
3720 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
\r
3721 #define CAN_F7R1_FB28_Pos (28U)
\r
3722 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
\r
3723 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
\r
3724 #define CAN_F7R1_FB29_Pos (29U)
\r
3725 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
\r
3726 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
\r
3727 #define CAN_F7R1_FB30_Pos (30U)
\r
3728 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
\r
3729 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
\r
3730 #define CAN_F7R1_FB31_Pos (31U)
\r
3731 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
\r
3732 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
\r
3734 /******************* Bit definition for CAN_F8R1 register *******************/
\r
3735 #define CAN_F8R1_FB0_Pos (0U)
\r
3736 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
\r
3737 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
\r
3738 #define CAN_F8R1_FB1_Pos (1U)
\r
3739 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
\r
3740 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
\r
3741 #define CAN_F8R1_FB2_Pos (2U)
\r
3742 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
\r
3743 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
\r
3744 #define CAN_F8R1_FB3_Pos (3U)
\r
3745 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
\r
3746 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
\r
3747 #define CAN_F8R1_FB4_Pos (4U)
\r
3748 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
\r
3749 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
\r
3750 #define CAN_F8R1_FB5_Pos (5U)
\r
3751 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
\r
3752 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
\r
3753 #define CAN_F8R1_FB6_Pos (6U)
\r
3754 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
\r
3755 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
\r
3756 #define CAN_F8R1_FB7_Pos (7U)
\r
3757 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
\r
3758 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
\r
3759 #define CAN_F8R1_FB8_Pos (8U)
\r
3760 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
\r
3761 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
\r
3762 #define CAN_F8R1_FB9_Pos (9U)
\r
3763 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
\r
3764 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
\r
3765 #define CAN_F8R1_FB10_Pos (10U)
\r
3766 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
\r
3767 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
\r
3768 #define CAN_F8R1_FB11_Pos (11U)
\r
3769 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
\r
3770 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
\r
3771 #define CAN_F8R1_FB12_Pos (12U)
\r
3772 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
\r
3773 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
\r
3774 #define CAN_F8R1_FB13_Pos (13U)
\r
3775 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
\r
3776 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
\r
3777 #define CAN_F8R1_FB14_Pos (14U)
\r
3778 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
\r
3779 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
\r
3780 #define CAN_F8R1_FB15_Pos (15U)
\r
3781 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
\r
3782 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
\r
3783 #define CAN_F8R1_FB16_Pos (16U)
\r
3784 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
\r
3785 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
\r
3786 #define CAN_F8R1_FB17_Pos (17U)
\r
3787 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
\r
3788 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
\r
3789 #define CAN_F8R1_FB18_Pos (18U)
\r
3790 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
\r
3791 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
\r
3792 #define CAN_F8R1_FB19_Pos (19U)
\r
3793 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
\r
3794 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
\r
3795 #define CAN_F8R1_FB20_Pos (20U)
\r
3796 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
\r
3797 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
\r
3798 #define CAN_F8R1_FB21_Pos (21U)
\r
3799 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
\r
3800 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
\r
3801 #define CAN_F8R1_FB22_Pos (22U)
\r
3802 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
\r
3803 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
\r
3804 #define CAN_F8R1_FB23_Pos (23U)
\r
3805 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
\r
3806 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
\r
3807 #define CAN_F8R1_FB24_Pos (24U)
\r
3808 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
\r
3809 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
\r
3810 #define CAN_F8R1_FB25_Pos (25U)
\r
3811 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
\r
3812 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
\r
3813 #define CAN_F8R1_FB26_Pos (26U)
\r
3814 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
\r
3815 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
\r
3816 #define CAN_F8R1_FB27_Pos (27U)
\r
3817 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
\r
3818 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
\r
3819 #define CAN_F8R1_FB28_Pos (28U)
\r
3820 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
\r
3821 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
\r
3822 #define CAN_F8R1_FB29_Pos (29U)
\r
3823 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
\r
3824 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
\r
3825 #define CAN_F8R1_FB30_Pos (30U)
\r
3826 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
\r
3827 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
\r
3828 #define CAN_F8R1_FB31_Pos (31U)
\r
3829 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
\r
3830 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
\r
3832 /******************* Bit definition for CAN_F9R1 register *******************/
\r
3833 #define CAN_F9R1_FB0_Pos (0U)
\r
3834 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
\r
3835 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
\r
3836 #define CAN_F9R1_FB1_Pos (1U)
\r
3837 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
\r
3838 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
\r
3839 #define CAN_F9R1_FB2_Pos (2U)
\r
3840 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
\r
3841 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
\r
3842 #define CAN_F9R1_FB3_Pos (3U)
\r
3843 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
\r
3844 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
\r
3845 #define CAN_F9R1_FB4_Pos (4U)
\r
3846 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
\r
3847 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
\r
3848 #define CAN_F9R1_FB5_Pos (5U)
\r
3849 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
\r
3850 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
\r
3851 #define CAN_F9R1_FB6_Pos (6U)
\r
3852 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
\r
3853 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
\r
3854 #define CAN_F9R1_FB7_Pos (7U)
\r
3855 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
\r
3856 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
\r
3857 #define CAN_F9R1_FB8_Pos (8U)
\r
3858 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
\r
3859 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
\r
3860 #define CAN_F9R1_FB9_Pos (9U)
\r
3861 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
\r
3862 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
\r
3863 #define CAN_F9R1_FB10_Pos (10U)
\r
3864 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
\r
3865 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
\r
3866 #define CAN_F9R1_FB11_Pos (11U)
\r
3867 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
\r
3868 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
\r
3869 #define CAN_F9R1_FB12_Pos (12U)
\r
3870 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
\r
3871 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
\r
3872 #define CAN_F9R1_FB13_Pos (13U)
\r
3873 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
\r
3874 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
\r
3875 #define CAN_F9R1_FB14_Pos (14U)
\r
3876 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
\r
3877 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
\r
3878 #define CAN_F9R1_FB15_Pos (15U)
\r
3879 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
\r
3880 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
\r
3881 #define CAN_F9R1_FB16_Pos (16U)
\r
3882 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
\r
3883 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
\r
3884 #define CAN_F9R1_FB17_Pos (17U)
\r
3885 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
\r
3886 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
\r
3887 #define CAN_F9R1_FB18_Pos (18U)
\r
3888 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
\r
3889 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
\r
3890 #define CAN_F9R1_FB19_Pos (19U)
\r
3891 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
\r
3892 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
\r
3893 #define CAN_F9R1_FB20_Pos (20U)
\r
3894 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
\r
3895 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
\r
3896 #define CAN_F9R1_FB21_Pos (21U)
\r
3897 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
\r
3898 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
\r
3899 #define CAN_F9R1_FB22_Pos (22U)
\r
3900 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
\r
3901 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
\r
3902 #define CAN_F9R1_FB23_Pos (23U)
\r
3903 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
\r
3904 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
\r
3905 #define CAN_F9R1_FB24_Pos (24U)
\r
3906 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
\r
3907 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
\r
3908 #define CAN_F9R1_FB25_Pos (25U)
\r
3909 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
\r
3910 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
\r
3911 #define CAN_F9R1_FB26_Pos (26U)
\r
3912 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
\r
3913 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
\r
3914 #define CAN_F9R1_FB27_Pos (27U)
\r
3915 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
\r
3916 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
\r
3917 #define CAN_F9R1_FB28_Pos (28U)
\r
3918 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
\r
3919 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
\r
3920 #define CAN_F9R1_FB29_Pos (29U)
\r
3921 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
\r
3922 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
\r
3923 #define CAN_F9R1_FB30_Pos (30U)
\r
3924 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
\r
3925 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
\r
3926 #define CAN_F9R1_FB31_Pos (31U)
\r
3927 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
\r
3928 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
\r
3930 /******************* Bit definition for CAN_F10R1 register ******************/
\r
3931 #define CAN_F10R1_FB0_Pos (0U)
\r
3932 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
\r
3933 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
\r
3934 #define CAN_F10R1_FB1_Pos (1U)
\r
3935 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
\r
3936 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
\r
3937 #define CAN_F10R1_FB2_Pos (2U)
\r
3938 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
\r
3939 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
\r
3940 #define CAN_F10R1_FB3_Pos (3U)
\r
3941 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
\r
3942 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
\r
3943 #define CAN_F10R1_FB4_Pos (4U)
\r
3944 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
\r
3945 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
\r
3946 #define CAN_F10R1_FB5_Pos (5U)
\r
3947 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
\r
3948 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
\r
3949 #define CAN_F10R1_FB6_Pos (6U)
\r
3950 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
\r
3951 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
\r
3952 #define CAN_F10R1_FB7_Pos (7U)
\r
3953 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
\r
3954 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
\r
3955 #define CAN_F10R1_FB8_Pos (8U)
\r
3956 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
\r
3957 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
\r
3958 #define CAN_F10R1_FB9_Pos (9U)
\r
3959 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
\r
3960 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
\r
3961 #define CAN_F10R1_FB10_Pos (10U)
\r
3962 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
\r
3963 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
\r
3964 #define CAN_F10R1_FB11_Pos (11U)
\r
3965 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
\r
3966 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
\r
3967 #define CAN_F10R1_FB12_Pos (12U)
\r
3968 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
\r
3969 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
\r
3970 #define CAN_F10R1_FB13_Pos (13U)
\r
3971 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
\r
3972 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
\r
3973 #define CAN_F10R1_FB14_Pos (14U)
\r
3974 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
\r
3975 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
\r
3976 #define CAN_F10R1_FB15_Pos (15U)
\r
3977 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
\r
3978 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
\r
3979 #define CAN_F10R1_FB16_Pos (16U)
\r
3980 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
\r
3981 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
\r
3982 #define CAN_F10R1_FB17_Pos (17U)
\r
3983 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
\r
3984 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
\r
3985 #define CAN_F10R1_FB18_Pos (18U)
\r
3986 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
\r
3987 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
\r
3988 #define CAN_F10R1_FB19_Pos (19U)
\r
3989 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
\r
3990 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
\r
3991 #define CAN_F10R1_FB20_Pos (20U)
\r
3992 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
\r
3993 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
\r
3994 #define CAN_F10R1_FB21_Pos (21U)
\r
3995 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
\r
3996 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
\r
3997 #define CAN_F10R1_FB22_Pos (22U)
\r
3998 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
\r
3999 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
\r
4000 #define CAN_F10R1_FB23_Pos (23U)
\r
4001 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
\r
4002 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
\r
4003 #define CAN_F10R1_FB24_Pos (24U)
\r
4004 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
\r
4005 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
\r
4006 #define CAN_F10R1_FB25_Pos (25U)
\r
4007 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
\r
4008 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
\r
4009 #define CAN_F10R1_FB26_Pos (26U)
\r
4010 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
\r
4011 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
\r
4012 #define CAN_F10R1_FB27_Pos (27U)
\r
4013 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
\r
4014 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
\r
4015 #define CAN_F10R1_FB28_Pos (28U)
\r
4016 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
\r
4017 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
\r
4018 #define CAN_F10R1_FB29_Pos (29U)
\r
4019 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
\r
4020 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
\r
4021 #define CAN_F10R1_FB30_Pos (30U)
\r
4022 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
\r
4023 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
\r
4024 #define CAN_F10R1_FB31_Pos (31U)
\r
4025 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
\r
4026 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
\r
4028 /******************* Bit definition for CAN_F11R1 register ******************/
\r
4029 #define CAN_F11R1_FB0_Pos (0U)
\r
4030 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
\r
4031 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
\r
4032 #define CAN_F11R1_FB1_Pos (1U)
\r
4033 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
\r
4034 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
\r
4035 #define CAN_F11R1_FB2_Pos (2U)
\r
4036 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
\r
4037 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
\r
4038 #define CAN_F11R1_FB3_Pos (3U)
\r
4039 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
\r
4040 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
\r
4041 #define CAN_F11R1_FB4_Pos (4U)
\r
4042 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
\r
4043 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
\r
4044 #define CAN_F11R1_FB5_Pos (5U)
\r
4045 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
\r
4046 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
\r
4047 #define CAN_F11R1_FB6_Pos (6U)
\r
4048 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
\r
4049 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
\r
4050 #define CAN_F11R1_FB7_Pos (7U)
\r
4051 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
\r
4052 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
\r
4053 #define CAN_F11R1_FB8_Pos (8U)
\r
4054 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
\r
4055 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
\r
4056 #define CAN_F11R1_FB9_Pos (9U)
\r
4057 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
\r
4058 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
\r
4059 #define CAN_F11R1_FB10_Pos (10U)
\r
4060 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
\r
4061 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
\r
4062 #define CAN_F11R1_FB11_Pos (11U)
\r
4063 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
\r
4064 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
\r
4065 #define CAN_F11R1_FB12_Pos (12U)
\r
4066 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
\r
4067 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
\r
4068 #define CAN_F11R1_FB13_Pos (13U)
\r
4069 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
\r
4070 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
\r
4071 #define CAN_F11R1_FB14_Pos (14U)
\r
4072 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
\r
4073 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
\r
4074 #define CAN_F11R1_FB15_Pos (15U)
\r
4075 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
\r
4076 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
\r
4077 #define CAN_F11R1_FB16_Pos (16U)
\r
4078 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
\r
4079 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
\r
4080 #define CAN_F11R1_FB17_Pos (17U)
\r
4081 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
\r
4082 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
\r
4083 #define CAN_F11R1_FB18_Pos (18U)
\r
4084 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
\r
4085 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
\r
4086 #define CAN_F11R1_FB19_Pos (19U)
\r
4087 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
\r
4088 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
\r
4089 #define CAN_F11R1_FB20_Pos (20U)
\r
4090 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
\r
4091 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
\r
4092 #define CAN_F11R1_FB21_Pos (21U)
\r
4093 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
\r
4094 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
\r
4095 #define CAN_F11R1_FB22_Pos (22U)
\r
4096 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
\r
4097 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
\r
4098 #define CAN_F11R1_FB23_Pos (23U)
\r
4099 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
\r
4100 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
\r
4101 #define CAN_F11R1_FB24_Pos (24U)
\r
4102 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
\r
4103 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
\r
4104 #define CAN_F11R1_FB25_Pos (25U)
\r
4105 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
\r
4106 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
\r
4107 #define CAN_F11R1_FB26_Pos (26U)
\r
4108 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
\r
4109 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
\r
4110 #define CAN_F11R1_FB27_Pos (27U)
\r
4111 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
\r
4112 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
\r
4113 #define CAN_F11R1_FB28_Pos (28U)
\r
4114 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
\r
4115 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
\r
4116 #define CAN_F11R1_FB29_Pos (29U)
\r
4117 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
\r
4118 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
\r
4119 #define CAN_F11R1_FB30_Pos (30U)
\r
4120 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
\r
4121 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
\r
4122 #define CAN_F11R1_FB31_Pos (31U)
\r
4123 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
\r
4124 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
\r
4126 /******************* Bit definition for CAN_F12R1 register ******************/
\r
4127 #define CAN_F12R1_FB0_Pos (0U)
\r
4128 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
\r
4129 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
\r
4130 #define CAN_F12R1_FB1_Pos (1U)
\r
4131 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
\r
4132 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
\r
4133 #define CAN_F12R1_FB2_Pos (2U)
\r
4134 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
\r
4135 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
\r
4136 #define CAN_F12R1_FB3_Pos (3U)
\r
4137 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
\r
4138 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
\r
4139 #define CAN_F12R1_FB4_Pos (4U)
\r
4140 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
\r
4141 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
\r
4142 #define CAN_F12R1_FB5_Pos (5U)
\r
4143 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
\r
4144 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
\r
4145 #define CAN_F12R1_FB6_Pos (6U)
\r
4146 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
\r
4147 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
\r
4148 #define CAN_F12R1_FB7_Pos (7U)
\r
4149 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
\r
4150 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
\r
4151 #define CAN_F12R1_FB8_Pos (8U)
\r
4152 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
\r
4153 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
\r
4154 #define CAN_F12R1_FB9_Pos (9U)
\r
4155 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
\r
4156 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
\r
4157 #define CAN_F12R1_FB10_Pos (10U)
\r
4158 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
\r
4159 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
\r
4160 #define CAN_F12R1_FB11_Pos (11U)
\r
4161 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
\r
4162 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
\r
4163 #define CAN_F12R1_FB12_Pos (12U)
\r
4164 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
\r
4165 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
\r
4166 #define CAN_F12R1_FB13_Pos (13U)
\r
4167 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
\r
4168 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
\r
4169 #define CAN_F12R1_FB14_Pos (14U)
\r
4170 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
\r
4171 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
\r
4172 #define CAN_F12R1_FB15_Pos (15U)
\r
4173 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
\r
4174 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
\r
4175 #define CAN_F12R1_FB16_Pos (16U)
\r
4176 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
\r
4177 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
\r
4178 #define CAN_F12R1_FB17_Pos (17U)
\r
4179 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
\r
4180 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
\r
4181 #define CAN_F12R1_FB18_Pos (18U)
\r
4182 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
\r
4183 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
\r
4184 #define CAN_F12R1_FB19_Pos (19U)
\r
4185 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
\r
4186 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
\r
4187 #define CAN_F12R1_FB20_Pos (20U)
\r
4188 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
\r
4189 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
\r
4190 #define CAN_F12R1_FB21_Pos (21U)
\r
4191 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
\r
4192 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
\r
4193 #define CAN_F12R1_FB22_Pos (22U)
\r
4194 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
\r
4195 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
\r
4196 #define CAN_F12R1_FB23_Pos (23U)
\r
4197 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
\r
4198 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
\r
4199 #define CAN_F12R1_FB24_Pos (24U)
\r
4200 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
\r
4201 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
\r
4202 #define CAN_F12R1_FB25_Pos (25U)
\r
4203 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
\r
4204 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
\r
4205 #define CAN_F12R1_FB26_Pos (26U)
\r
4206 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
\r
4207 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
\r
4208 #define CAN_F12R1_FB27_Pos (27U)
\r
4209 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
\r
4210 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
\r
4211 #define CAN_F12R1_FB28_Pos (28U)
\r
4212 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
\r
4213 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
\r
4214 #define CAN_F12R1_FB29_Pos (29U)
\r
4215 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
\r
4216 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
\r
4217 #define CAN_F12R1_FB30_Pos (30U)
\r
4218 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
\r
4219 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
\r
4220 #define CAN_F12R1_FB31_Pos (31U)
\r
4221 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
\r
4222 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
\r
4224 /******************* Bit definition for CAN_F13R1 register ******************/
\r
4225 #define CAN_F13R1_FB0_Pos (0U)
\r
4226 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
\r
4227 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
\r
4228 #define CAN_F13R1_FB1_Pos (1U)
\r
4229 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
\r
4230 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
\r
4231 #define CAN_F13R1_FB2_Pos (2U)
\r
4232 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
\r
4233 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
\r
4234 #define CAN_F13R1_FB3_Pos (3U)
\r
4235 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
\r
4236 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
\r
4237 #define CAN_F13R1_FB4_Pos (4U)
\r
4238 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
\r
4239 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
\r
4240 #define CAN_F13R1_FB5_Pos (5U)
\r
4241 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
\r
4242 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
\r
4243 #define CAN_F13R1_FB6_Pos (6U)
\r
4244 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
\r
4245 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
\r
4246 #define CAN_F13R1_FB7_Pos (7U)
\r
4247 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
\r
4248 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
\r
4249 #define CAN_F13R1_FB8_Pos (8U)
\r
4250 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
\r
4251 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
\r
4252 #define CAN_F13R1_FB9_Pos (9U)
\r
4253 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
\r
4254 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
\r
4255 #define CAN_F13R1_FB10_Pos (10U)
\r
4256 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
\r
4257 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
\r
4258 #define CAN_F13R1_FB11_Pos (11U)
\r
4259 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
\r
4260 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
\r
4261 #define CAN_F13R1_FB12_Pos (12U)
\r
4262 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
\r
4263 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
\r
4264 #define CAN_F13R1_FB13_Pos (13U)
\r
4265 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
\r
4266 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
\r
4267 #define CAN_F13R1_FB14_Pos (14U)
\r
4268 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
\r
4269 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
\r
4270 #define CAN_F13R1_FB15_Pos (15U)
\r
4271 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
\r
4272 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
\r
4273 #define CAN_F13R1_FB16_Pos (16U)
\r
4274 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
\r
4275 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
\r
4276 #define CAN_F13R1_FB17_Pos (17U)
\r
4277 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
\r
4278 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
\r
4279 #define CAN_F13R1_FB18_Pos (18U)
\r
4280 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
\r
4281 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
\r
4282 #define CAN_F13R1_FB19_Pos (19U)
\r
4283 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
\r
4284 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
\r
4285 #define CAN_F13R1_FB20_Pos (20U)
\r
4286 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
\r
4287 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
\r
4288 #define CAN_F13R1_FB21_Pos (21U)
\r
4289 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
\r
4290 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
\r
4291 #define CAN_F13R1_FB22_Pos (22U)
\r
4292 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
\r
4293 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
\r
4294 #define CAN_F13R1_FB23_Pos (23U)
\r
4295 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
\r
4296 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
\r
4297 #define CAN_F13R1_FB24_Pos (24U)
\r
4298 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
\r
4299 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
\r
4300 #define CAN_F13R1_FB25_Pos (25U)
\r
4301 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
\r
4302 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
\r
4303 #define CAN_F13R1_FB26_Pos (26U)
\r
4304 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
\r
4305 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
\r
4306 #define CAN_F13R1_FB27_Pos (27U)
\r
4307 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
\r
4308 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
\r
4309 #define CAN_F13R1_FB28_Pos (28U)
\r
4310 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
\r
4311 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
\r
4312 #define CAN_F13R1_FB29_Pos (29U)
\r
4313 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
\r
4314 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
\r
4315 #define CAN_F13R1_FB30_Pos (30U)
\r
4316 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
\r
4317 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
\r
4318 #define CAN_F13R1_FB31_Pos (31U)
\r
4319 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
\r
4320 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
\r
4322 /******************* Bit definition for CAN_F0R2 register *******************/
\r
4323 #define CAN_F0R2_FB0_Pos (0U)
\r
4324 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
\r
4325 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
\r
4326 #define CAN_F0R2_FB1_Pos (1U)
\r
4327 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
\r
4328 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
\r
4329 #define CAN_F0R2_FB2_Pos (2U)
\r
4330 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
\r
4331 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
\r
4332 #define CAN_F0R2_FB3_Pos (3U)
\r
4333 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
\r
4334 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
\r
4335 #define CAN_F0R2_FB4_Pos (4U)
\r
4336 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
\r
4337 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
\r
4338 #define CAN_F0R2_FB5_Pos (5U)
\r
4339 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
\r
4340 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
\r
4341 #define CAN_F0R2_FB6_Pos (6U)
\r
4342 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
\r
4343 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
\r
4344 #define CAN_F0R2_FB7_Pos (7U)
\r
4345 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
\r
4346 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
\r
4347 #define CAN_F0R2_FB8_Pos (8U)
\r
4348 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
\r
4349 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
\r
4350 #define CAN_F0R2_FB9_Pos (9U)
\r
4351 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
\r
4352 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
\r
4353 #define CAN_F0R2_FB10_Pos (10U)
\r
4354 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
\r
4355 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
\r
4356 #define CAN_F0R2_FB11_Pos (11U)
\r
4357 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
\r
4358 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
\r
4359 #define CAN_F0R2_FB12_Pos (12U)
\r
4360 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
\r
4361 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
\r
4362 #define CAN_F0R2_FB13_Pos (13U)
\r
4363 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
\r
4364 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
\r
4365 #define CAN_F0R2_FB14_Pos (14U)
\r
4366 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
\r
4367 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
\r
4368 #define CAN_F0R2_FB15_Pos (15U)
\r
4369 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
\r
4370 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
\r
4371 #define CAN_F0R2_FB16_Pos (16U)
\r
4372 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
\r
4373 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
\r
4374 #define CAN_F0R2_FB17_Pos (17U)
\r
4375 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
\r
4376 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
\r
4377 #define CAN_F0R2_FB18_Pos (18U)
\r
4378 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
\r
4379 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
\r
4380 #define CAN_F0R2_FB19_Pos (19U)
\r
4381 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
\r
4382 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
\r
4383 #define CAN_F0R2_FB20_Pos (20U)
\r
4384 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
\r
4385 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
\r
4386 #define CAN_F0R2_FB21_Pos (21U)
\r
4387 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
\r
4388 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
\r
4389 #define CAN_F0R2_FB22_Pos (22U)
\r
4390 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
\r
4391 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
\r
4392 #define CAN_F0R2_FB23_Pos (23U)
\r
4393 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
\r
4394 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
\r
4395 #define CAN_F0R2_FB24_Pos (24U)
\r
4396 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
\r
4397 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
\r
4398 #define CAN_F0R2_FB25_Pos (25U)
\r
4399 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
\r
4400 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
\r
4401 #define CAN_F0R2_FB26_Pos (26U)
\r
4402 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
\r
4403 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
\r
4404 #define CAN_F0R2_FB27_Pos (27U)
\r
4405 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
\r
4406 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
\r
4407 #define CAN_F0R2_FB28_Pos (28U)
\r
4408 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
\r
4409 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
\r
4410 #define CAN_F0R2_FB29_Pos (29U)
\r
4411 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
\r
4412 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
\r
4413 #define CAN_F0R2_FB30_Pos (30U)
\r
4414 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
\r
4415 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
\r
4416 #define CAN_F0R2_FB31_Pos (31U)
\r
4417 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
\r
4418 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
\r
4420 /******************* Bit definition for CAN_F1R2 register *******************/
\r
4421 #define CAN_F1R2_FB0_Pos (0U)
\r
4422 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
\r
4423 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
\r
4424 #define CAN_F1R2_FB1_Pos (1U)
\r
4425 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
\r
4426 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
\r
4427 #define CAN_F1R2_FB2_Pos (2U)
\r
4428 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
\r
4429 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
\r
4430 #define CAN_F1R2_FB3_Pos (3U)
\r
4431 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
\r
4432 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
\r
4433 #define CAN_F1R2_FB4_Pos (4U)
\r
4434 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
\r
4435 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
\r
4436 #define CAN_F1R2_FB5_Pos (5U)
\r
4437 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
\r
4438 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
\r
4439 #define CAN_F1R2_FB6_Pos (6U)
\r
4440 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
\r
4441 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
\r
4442 #define CAN_F1R2_FB7_Pos (7U)
\r
4443 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
\r
4444 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
\r
4445 #define CAN_F1R2_FB8_Pos (8U)
\r
4446 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
\r
4447 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
\r
4448 #define CAN_F1R2_FB9_Pos (9U)
\r
4449 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
\r
4450 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
\r
4451 #define CAN_F1R2_FB10_Pos (10U)
\r
4452 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
\r
4453 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
\r
4454 #define CAN_F1R2_FB11_Pos (11U)
\r
4455 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
\r
4456 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
\r
4457 #define CAN_F1R2_FB12_Pos (12U)
\r
4458 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
\r
4459 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
\r
4460 #define CAN_F1R2_FB13_Pos (13U)
\r
4461 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
\r
4462 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
\r
4463 #define CAN_F1R2_FB14_Pos (14U)
\r
4464 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
\r
4465 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
\r
4466 #define CAN_F1R2_FB15_Pos (15U)
\r
4467 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
\r
4468 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
\r
4469 #define CAN_F1R2_FB16_Pos (16U)
\r
4470 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
\r
4471 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
\r
4472 #define CAN_F1R2_FB17_Pos (17U)
\r
4473 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
\r
4474 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
\r
4475 #define CAN_F1R2_FB18_Pos (18U)
\r
4476 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
\r
4477 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
\r
4478 #define CAN_F1R2_FB19_Pos (19U)
\r
4479 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
\r
4480 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
\r
4481 #define CAN_F1R2_FB20_Pos (20U)
\r
4482 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
\r
4483 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
\r
4484 #define CAN_F1R2_FB21_Pos (21U)
\r
4485 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
\r
4486 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
\r
4487 #define CAN_F1R2_FB22_Pos (22U)
\r
4488 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
\r
4489 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
\r
4490 #define CAN_F1R2_FB23_Pos (23U)
\r
4491 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
\r
4492 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
\r
4493 #define CAN_F1R2_FB24_Pos (24U)
\r
4494 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
\r
4495 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
\r
4496 #define CAN_F1R2_FB25_Pos (25U)
\r
4497 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
\r
4498 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
\r
4499 #define CAN_F1R2_FB26_Pos (26U)
\r
4500 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
\r
4501 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
\r
4502 #define CAN_F1R2_FB27_Pos (27U)
\r
4503 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
\r
4504 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
\r
4505 #define CAN_F1R2_FB28_Pos (28U)
\r
4506 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
\r
4507 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
\r
4508 #define CAN_F1R2_FB29_Pos (29U)
\r
4509 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
\r
4510 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
\r
4511 #define CAN_F1R2_FB30_Pos (30U)
\r
4512 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
\r
4513 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
\r
4514 #define CAN_F1R2_FB31_Pos (31U)
\r
4515 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
\r
4516 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
\r
4518 /******************* Bit definition for CAN_F2R2 register *******************/
\r
4519 #define CAN_F2R2_FB0_Pos (0U)
\r
4520 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
\r
4521 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
\r
4522 #define CAN_F2R2_FB1_Pos (1U)
\r
4523 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
\r
4524 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
\r
4525 #define CAN_F2R2_FB2_Pos (2U)
\r
4526 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
\r
4527 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
\r
4528 #define CAN_F2R2_FB3_Pos (3U)
\r
4529 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
\r
4530 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
\r
4531 #define CAN_F2R2_FB4_Pos (4U)
\r
4532 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
\r
4533 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
\r
4534 #define CAN_F2R2_FB5_Pos (5U)
\r
4535 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
\r
4536 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
\r
4537 #define CAN_F2R2_FB6_Pos (6U)
\r
4538 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
\r
4539 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
\r
4540 #define CAN_F2R2_FB7_Pos (7U)
\r
4541 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
\r
4542 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
\r
4543 #define CAN_F2R2_FB8_Pos (8U)
\r
4544 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
\r
4545 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
\r
4546 #define CAN_F2R2_FB9_Pos (9U)
\r
4547 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
\r
4548 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
\r
4549 #define CAN_F2R2_FB10_Pos (10U)
\r
4550 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
\r
4551 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
\r
4552 #define CAN_F2R2_FB11_Pos (11U)
\r
4553 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
\r
4554 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
\r
4555 #define CAN_F2R2_FB12_Pos (12U)
\r
4556 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
\r
4557 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
\r
4558 #define CAN_F2R2_FB13_Pos (13U)
\r
4559 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
\r
4560 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
\r
4561 #define CAN_F2R2_FB14_Pos (14U)
\r
4562 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
\r
4563 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
\r
4564 #define CAN_F2R2_FB15_Pos (15U)
\r
4565 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
\r
4566 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
\r
4567 #define CAN_F2R2_FB16_Pos (16U)
\r
4568 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
\r
4569 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
\r
4570 #define CAN_F2R2_FB17_Pos (17U)
\r
4571 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
\r
4572 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
\r
4573 #define CAN_F2R2_FB18_Pos (18U)
\r
4574 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
\r
4575 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
\r
4576 #define CAN_F2R2_FB19_Pos (19U)
\r
4577 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
\r
4578 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
\r
4579 #define CAN_F2R2_FB20_Pos (20U)
\r
4580 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
\r
4581 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
\r
4582 #define CAN_F2R2_FB21_Pos (21U)
\r
4583 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
\r
4584 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
\r
4585 #define CAN_F2R2_FB22_Pos (22U)
\r
4586 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
\r
4587 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
\r
4588 #define CAN_F2R2_FB23_Pos (23U)
\r
4589 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
\r
4590 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
\r
4591 #define CAN_F2R2_FB24_Pos (24U)
\r
4592 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
\r
4593 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
\r
4594 #define CAN_F2R2_FB25_Pos (25U)
\r
4595 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
\r
4596 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
\r
4597 #define CAN_F2R2_FB26_Pos (26U)
\r
4598 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
\r
4599 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
\r
4600 #define CAN_F2R2_FB27_Pos (27U)
\r
4601 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
\r
4602 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
\r
4603 #define CAN_F2R2_FB28_Pos (28U)
\r
4604 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
\r
4605 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
\r
4606 #define CAN_F2R2_FB29_Pos (29U)
\r
4607 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
\r
4608 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
\r
4609 #define CAN_F2R2_FB30_Pos (30U)
\r
4610 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
\r
4611 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
\r
4612 #define CAN_F2R2_FB31_Pos (31U)
\r
4613 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
\r
4614 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
\r
4616 /******************* Bit definition for CAN_F3R2 register *******************/
\r
4617 #define CAN_F3R2_FB0_Pos (0U)
\r
4618 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
\r
4619 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
\r
4620 #define CAN_F3R2_FB1_Pos (1U)
\r
4621 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
\r
4622 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
\r
4623 #define CAN_F3R2_FB2_Pos (2U)
\r
4624 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
\r
4625 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
\r
4626 #define CAN_F3R2_FB3_Pos (3U)
\r
4627 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
\r
4628 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
\r
4629 #define CAN_F3R2_FB4_Pos (4U)
\r
4630 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
\r
4631 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
\r
4632 #define CAN_F3R2_FB5_Pos (5U)
\r
4633 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
\r
4634 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
\r
4635 #define CAN_F3R2_FB6_Pos (6U)
\r
4636 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
\r
4637 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
\r
4638 #define CAN_F3R2_FB7_Pos (7U)
\r
4639 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
\r
4640 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
\r
4641 #define CAN_F3R2_FB8_Pos (8U)
\r
4642 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
\r
4643 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
\r
4644 #define CAN_F3R2_FB9_Pos (9U)
\r
4645 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
\r
4646 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
\r
4647 #define CAN_F3R2_FB10_Pos (10U)
\r
4648 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
\r
4649 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
\r
4650 #define CAN_F3R2_FB11_Pos (11U)
\r
4651 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
\r
4652 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
\r
4653 #define CAN_F3R2_FB12_Pos (12U)
\r
4654 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
\r
4655 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
\r
4656 #define CAN_F3R2_FB13_Pos (13U)
\r
4657 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
\r
4658 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
\r
4659 #define CAN_F3R2_FB14_Pos (14U)
\r
4660 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
\r
4661 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
\r
4662 #define CAN_F3R2_FB15_Pos (15U)
\r
4663 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
\r
4664 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
\r
4665 #define CAN_F3R2_FB16_Pos (16U)
\r
4666 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
\r
4667 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
\r
4668 #define CAN_F3R2_FB17_Pos (17U)
\r
4669 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
\r
4670 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
\r
4671 #define CAN_F3R2_FB18_Pos (18U)
\r
4672 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
\r
4673 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
\r
4674 #define CAN_F3R2_FB19_Pos (19U)
\r
4675 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
\r
4676 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
\r
4677 #define CAN_F3R2_FB20_Pos (20U)
\r
4678 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
\r
4679 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
\r
4680 #define CAN_F3R2_FB21_Pos (21U)
\r
4681 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
\r
4682 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
\r
4683 #define CAN_F3R2_FB22_Pos (22U)
\r
4684 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
\r
4685 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
\r
4686 #define CAN_F3R2_FB23_Pos (23U)
\r
4687 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
\r
4688 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
\r
4689 #define CAN_F3R2_FB24_Pos (24U)
\r
4690 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
\r
4691 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
\r
4692 #define CAN_F3R2_FB25_Pos (25U)
\r
4693 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
\r
4694 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
\r
4695 #define CAN_F3R2_FB26_Pos (26U)
\r
4696 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
\r
4697 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
\r
4698 #define CAN_F3R2_FB27_Pos (27U)
\r
4699 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
\r
4700 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
\r
4701 #define CAN_F3R2_FB28_Pos (28U)
\r
4702 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
\r
4703 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
\r
4704 #define CAN_F3R2_FB29_Pos (29U)
\r
4705 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
\r
4706 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
\r
4707 #define CAN_F3R2_FB30_Pos (30U)
\r
4708 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
\r
4709 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
\r
4710 #define CAN_F3R2_FB31_Pos (31U)
\r
4711 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
\r
4712 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
\r
4714 /******************* Bit definition for CAN_F4R2 register *******************/
\r
4715 #define CAN_F4R2_FB0_Pos (0U)
\r
4716 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
\r
4717 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
\r
4718 #define CAN_F4R2_FB1_Pos (1U)
\r
4719 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
\r
4720 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
\r
4721 #define CAN_F4R2_FB2_Pos (2U)
\r
4722 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
\r
4723 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
\r
4724 #define CAN_F4R2_FB3_Pos (3U)
\r
4725 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
\r
4726 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
\r
4727 #define CAN_F4R2_FB4_Pos (4U)
\r
4728 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
\r
4729 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
\r
4730 #define CAN_F4R2_FB5_Pos (5U)
\r
4731 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
\r
4732 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
\r
4733 #define CAN_F4R2_FB6_Pos (6U)
\r
4734 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
\r
4735 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
\r
4736 #define CAN_F4R2_FB7_Pos (7U)
\r
4737 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
\r
4738 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
\r
4739 #define CAN_F4R2_FB8_Pos (8U)
\r
4740 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
\r
4741 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
\r
4742 #define CAN_F4R2_FB9_Pos (9U)
\r
4743 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
\r
4744 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
\r
4745 #define CAN_F4R2_FB10_Pos (10U)
\r
4746 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
\r
4747 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
\r
4748 #define CAN_F4R2_FB11_Pos (11U)
\r
4749 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
\r
4750 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
\r
4751 #define CAN_F4R2_FB12_Pos (12U)
\r
4752 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
\r
4753 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
\r
4754 #define CAN_F4R2_FB13_Pos (13U)
\r
4755 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
\r
4756 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
\r
4757 #define CAN_F4R2_FB14_Pos (14U)
\r
4758 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
\r
4759 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
\r
4760 #define CAN_F4R2_FB15_Pos (15U)
\r
4761 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
\r
4762 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
\r
4763 #define CAN_F4R2_FB16_Pos (16U)
\r
4764 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
\r
4765 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
\r
4766 #define CAN_F4R2_FB17_Pos (17U)
\r
4767 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
\r
4768 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
\r
4769 #define CAN_F4R2_FB18_Pos (18U)
\r
4770 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
\r
4771 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
\r
4772 #define CAN_F4R2_FB19_Pos (19U)
\r
4773 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
\r
4774 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
\r
4775 #define CAN_F4R2_FB20_Pos (20U)
\r
4776 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
\r
4777 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
\r
4778 #define CAN_F4R2_FB21_Pos (21U)
\r
4779 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
\r
4780 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
\r
4781 #define CAN_F4R2_FB22_Pos (22U)
\r
4782 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
\r
4783 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
\r
4784 #define CAN_F4R2_FB23_Pos (23U)
\r
4785 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
\r
4786 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
\r
4787 #define CAN_F4R2_FB24_Pos (24U)
\r
4788 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
\r
4789 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
\r
4790 #define CAN_F4R2_FB25_Pos (25U)
\r
4791 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
\r
4792 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
\r
4793 #define CAN_F4R2_FB26_Pos (26U)
\r
4794 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
\r
4795 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
\r
4796 #define CAN_F4R2_FB27_Pos (27U)
\r
4797 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
\r
4798 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
\r
4799 #define CAN_F4R2_FB28_Pos (28U)
\r
4800 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
\r
4801 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
\r
4802 #define CAN_F4R2_FB29_Pos (29U)
\r
4803 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
\r
4804 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
\r
4805 #define CAN_F4R2_FB30_Pos (30U)
\r
4806 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
\r
4807 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
\r
4808 #define CAN_F4R2_FB31_Pos (31U)
\r
4809 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
\r
4810 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
\r
4812 /******************* Bit definition for CAN_F5R2 register *******************/
\r
4813 #define CAN_F5R2_FB0_Pos (0U)
\r
4814 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
\r
4815 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
\r
4816 #define CAN_F5R2_FB1_Pos (1U)
\r
4817 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
\r
4818 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
\r
4819 #define CAN_F5R2_FB2_Pos (2U)
\r
4820 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
\r
4821 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
\r
4822 #define CAN_F5R2_FB3_Pos (3U)
\r
4823 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
\r
4824 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
\r
4825 #define CAN_F5R2_FB4_Pos (4U)
\r
4826 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
\r
4827 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
\r
4828 #define CAN_F5R2_FB5_Pos (5U)
\r
4829 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
\r
4830 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
\r
4831 #define CAN_F5R2_FB6_Pos (6U)
\r
4832 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
\r
4833 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
\r
4834 #define CAN_F5R2_FB7_Pos (7U)
\r
4835 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
\r
4836 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
\r
4837 #define CAN_F5R2_FB8_Pos (8U)
\r
4838 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
\r
4839 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
\r
4840 #define CAN_F5R2_FB9_Pos (9U)
\r
4841 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
\r
4842 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
\r
4843 #define CAN_F5R2_FB10_Pos (10U)
\r
4844 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
\r
4845 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
\r
4846 #define CAN_F5R2_FB11_Pos (11U)
\r
4847 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
\r
4848 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
\r
4849 #define CAN_F5R2_FB12_Pos (12U)
\r
4850 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
\r
4851 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
\r
4852 #define CAN_F5R2_FB13_Pos (13U)
\r
4853 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
\r
4854 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
\r
4855 #define CAN_F5R2_FB14_Pos (14U)
\r
4856 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
\r
4857 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
\r
4858 #define CAN_F5R2_FB15_Pos (15U)
\r
4859 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
\r
4860 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
\r
4861 #define CAN_F5R2_FB16_Pos (16U)
\r
4862 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
\r
4863 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
\r
4864 #define CAN_F5R2_FB17_Pos (17U)
\r
4865 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
\r
4866 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
\r
4867 #define CAN_F5R2_FB18_Pos (18U)
\r
4868 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
\r
4869 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
\r
4870 #define CAN_F5R2_FB19_Pos (19U)
\r
4871 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
\r
4872 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
\r
4873 #define CAN_F5R2_FB20_Pos (20U)
\r
4874 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
\r
4875 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
\r
4876 #define CAN_F5R2_FB21_Pos (21U)
\r
4877 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
\r
4878 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
\r
4879 #define CAN_F5R2_FB22_Pos (22U)
\r
4880 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
\r
4881 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
\r
4882 #define CAN_F5R2_FB23_Pos (23U)
\r
4883 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
\r
4884 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
\r
4885 #define CAN_F5R2_FB24_Pos (24U)
\r
4886 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
\r
4887 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
\r
4888 #define CAN_F5R2_FB25_Pos (25U)
\r
4889 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
\r
4890 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
\r
4891 #define CAN_F5R2_FB26_Pos (26U)
\r
4892 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
\r
4893 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
\r
4894 #define CAN_F5R2_FB27_Pos (27U)
\r
4895 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
\r
4896 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
\r
4897 #define CAN_F5R2_FB28_Pos (28U)
\r
4898 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
\r
4899 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
\r
4900 #define CAN_F5R2_FB29_Pos (29U)
\r
4901 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
\r
4902 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
\r
4903 #define CAN_F5R2_FB30_Pos (30U)
\r
4904 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
\r
4905 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
\r
4906 #define CAN_F5R2_FB31_Pos (31U)
\r
4907 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
\r
4908 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
\r
4910 /******************* Bit definition for CAN_F6R2 register *******************/
\r
4911 #define CAN_F6R2_FB0_Pos (0U)
\r
4912 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
\r
4913 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
\r
4914 #define CAN_F6R2_FB1_Pos (1U)
\r
4915 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
\r
4916 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
\r
4917 #define CAN_F6R2_FB2_Pos (2U)
\r
4918 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
\r
4919 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
\r
4920 #define CAN_F6R2_FB3_Pos (3U)
\r
4921 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
\r
4922 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
\r
4923 #define CAN_F6R2_FB4_Pos (4U)
\r
4924 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
\r
4925 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
\r
4926 #define CAN_F6R2_FB5_Pos (5U)
\r
4927 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
\r
4928 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
\r
4929 #define CAN_F6R2_FB6_Pos (6U)
\r
4930 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
\r
4931 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
\r
4932 #define CAN_F6R2_FB7_Pos (7U)
\r
4933 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
\r
4934 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
\r
4935 #define CAN_F6R2_FB8_Pos (8U)
\r
4936 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
\r
4937 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
\r
4938 #define CAN_F6R2_FB9_Pos (9U)
\r
4939 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
\r
4940 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
\r
4941 #define CAN_F6R2_FB10_Pos (10U)
\r
4942 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
\r
4943 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
\r
4944 #define CAN_F6R2_FB11_Pos (11U)
\r
4945 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
\r
4946 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
\r
4947 #define CAN_F6R2_FB12_Pos (12U)
\r
4948 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
\r
4949 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
\r
4950 #define CAN_F6R2_FB13_Pos (13U)
\r
4951 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
\r
4952 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
\r
4953 #define CAN_F6R2_FB14_Pos (14U)
\r
4954 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
\r
4955 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
\r
4956 #define CAN_F6R2_FB15_Pos (15U)
\r
4957 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
\r
4958 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
\r
4959 #define CAN_F6R2_FB16_Pos (16U)
\r
4960 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
\r
4961 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
\r
4962 #define CAN_F6R2_FB17_Pos (17U)
\r
4963 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
\r
4964 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
\r
4965 #define CAN_F6R2_FB18_Pos (18U)
\r
4966 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
\r
4967 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
\r
4968 #define CAN_F6R2_FB19_Pos (19U)
\r
4969 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
\r
4970 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
\r
4971 #define CAN_F6R2_FB20_Pos (20U)
\r
4972 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
\r
4973 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
\r
4974 #define CAN_F6R2_FB21_Pos (21U)
\r
4975 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
\r
4976 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
\r
4977 #define CAN_F6R2_FB22_Pos (22U)
\r
4978 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
\r
4979 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
\r
4980 #define CAN_F6R2_FB23_Pos (23U)
\r
4981 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
\r
4982 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
\r
4983 #define CAN_F6R2_FB24_Pos (24U)
\r
4984 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
\r
4985 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
\r
4986 #define CAN_F6R2_FB25_Pos (25U)
\r
4987 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
\r
4988 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
\r
4989 #define CAN_F6R2_FB26_Pos (26U)
\r
4990 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
\r
4991 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
\r
4992 #define CAN_F6R2_FB27_Pos (27U)
\r
4993 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
\r
4994 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
\r
4995 #define CAN_F6R2_FB28_Pos (28U)
\r
4996 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
\r
4997 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
\r
4998 #define CAN_F6R2_FB29_Pos (29U)
\r
4999 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
\r
5000 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
\r
5001 #define CAN_F6R2_FB30_Pos (30U)
\r
5002 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
\r
5003 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
\r
5004 #define CAN_F6R2_FB31_Pos (31U)
\r
5005 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
\r
5006 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
\r
5008 /******************* Bit definition for CAN_F7R2 register *******************/
\r
5009 #define CAN_F7R2_FB0_Pos (0U)
\r
5010 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
\r
5011 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
\r
5012 #define CAN_F7R2_FB1_Pos (1U)
\r
5013 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
\r
5014 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
\r
5015 #define CAN_F7R2_FB2_Pos (2U)
\r
5016 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
\r
5017 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
\r
5018 #define CAN_F7R2_FB3_Pos (3U)
\r
5019 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
\r
5020 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
\r
5021 #define CAN_F7R2_FB4_Pos (4U)
\r
5022 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
\r
5023 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
\r
5024 #define CAN_F7R2_FB5_Pos (5U)
\r
5025 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
\r
5026 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
\r
5027 #define CAN_F7R2_FB6_Pos (6U)
\r
5028 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
\r
5029 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
\r
5030 #define CAN_F7R2_FB7_Pos (7U)
\r
5031 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
\r
5032 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
\r
5033 #define CAN_F7R2_FB8_Pos (8U)
\r
5034 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
\r
5035 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
\r
5036 #define CAN_F7R2_FB9_Pos (9U)
\r
5037 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
\r
5038 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
\r
5039 #define CAN_F7R2_FB10_Pos (10U)
\r
5040 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
\r
5041 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
\r
5042 #define CAN_F7R2_FB11_Pos (11U)
\r
5043 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
\r
5044 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
\r
5045 #define CAN_F7R2_FB12_Pos (12U)
\r
5046 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
\r
5047 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
\r
5048 #define CAN_F7R2_FB13_Pos (13U)
\r
5049 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
\r
5050 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
\r
5051 #define CAN_F7R2_FB14_Pos (14U)
\r
5052 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
\r
5053 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
\r
5054 #define CAN_F7R2_FB15_Pos (15U)
\r
5055 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
\r
5056 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
\r
5057 #define CAN_F7R2_FB16_Pos (16U)
\r
5058 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
\r
5059 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
\r
5060 #define CAN_F7R2_FB17_Pos (17U)
\r
5061 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
\r
5062 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
\r
5063 #define CAN_F7R2_FB18_Pos (18U)
\r
5064 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
\r
5065 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
\r
5066 #define CAN_F7R2_FB19_Pos (19U)
\r
5067 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
\r
5068 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
\r
5069 #define CAN_F7R2_FB20_Pos (20U)
\r
5070 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
\r
5071 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
\r
5072 #define CAN_F7R2_FB21_Pos (21U)
\r
5073 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
\r
5074 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
\r
5075 #define CAN_F7R2_FB22_Pos (22U)
\r
5076 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
\r
5077 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
\r
5078 #define CAN_F7R2_FB23_Pos (23U)
\r
5079 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
\r
5080 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
\r
5081 #define CAN_F7R2_FB24_Pos (24U)
\r
5082 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
\r
5083 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
\r
5084 #define CAN_F7R2_FB25_Pos (25U)
\r
5085 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
\r
5086 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
\r
5087 #define CAN_F7R2_FB26_Pos (26U)
\r
5088 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
\r
5089 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
\r
5090 #define CAN_F7R2_FB27_Pos (27U)
\r
5091 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
\r
5092 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
\r
5093 #define CAN_F7R2_FB28_Pos (28U)
\r
5094 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
\r
5095 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
\r
5096 #define CAN_F7R2_FB29_Pos (29U)
\r
5097 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
\r
5098 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
\r
5099 #define CAN_F7R2_FB30_Pos (30U)
\r
5100 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
\r
5101 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
\r
5102 #define CAN_F7R2_FB31_Pos (31U)
\r
5103 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
\r
5104 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
\r
5106 /******************* Bit definition for CAN_F8R2 register *******************/
\r
5107 #define CAN_F8R2_FB0_Pos (0U)
\r
5108 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
\r
5109 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
\r
5110 #define CAN_F8R2_FB1_Pos (1U)
\r
5111 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
\r
5112 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
\r
5113 #define CAN_F8R2_FB2_Pos (2U)
\r
5114 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
\r
5115 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
\r
5116 #define CAN_F8R2_FB3_Pos (3U)
\r
5117 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
\r
5118 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
\r
5119 #define CAN_F8R2_FB4_Pos (4U)
\r
5120 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
\r
5121 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
\r
5122 #define CAN_F8R2_FB5_Pos (5U)
\r
5123 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
\r
5124 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
\r
5125 #define CAN_F8R2_FB6_Pos (6U)
\r
5126 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
\r
5127 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
\r
5128 #define CAN_F8R2_FB7_Pos (7U)
\r
5129 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
\r
5130 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
\r
5131 #define CAN_F8R2_FB8_Pos (8U)
\r
5132 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
\r
5133 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
\r
5134 #define CAN_F8R2_FB9_Pos (9U)
\r
5135 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
\r
5136 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
\r
5137 #define CAN_F8R2_FB10_Pos (10U)
\r
5138 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
\r
5139 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
\r
5140 #define CAN_F8R2_FB11_Pos (11U)
\r
5141 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
\r
5142 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
\r
5143 #define CAN_F8R2_FB12_Pos (12U)
\r
5144 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
\r
5145 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
\r
5146 #define CAN_F8R2_FB13_Pos (13U)
\r
5147 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
\r
5148 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
\r
5149 #define CAN_F8R2_FB14_Pos (14U)
\r
5150 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
\r
5151 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
\r
5152 #define CAN_F8R2_FB15_Pos (15U)
\r
5153 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
\r
5154 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
\r
5155 #define CAN_F8R2_FB16_Pos (16U)
\r
5156 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
\r
5157 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
\r
5158 #define CAN_F8R2_FB17_Pos (17U)
\r
5159 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
\r
5160 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
\r
5161 #define CAN_F8R2_FB18_Pos (18U)
\r
5162 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
\r
5163 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
\r
5164 #define CAN_F8R2_FB19_Pos (19U)
\r
5165 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
\r
5166 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
\r
5167 #define CAN_F8R2_FB20_Pos (20U)
\r
5168 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
\r
5169 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
\r
5170 #define CAN_F8R2_FB21_Pos (21U)
\r
5171 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
\r
5172 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
\r
5173 #define CAN_F8R2_FB22_Pos (22U)
\r
5174 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
\r
5175 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
\r
5176 #define CAN_F8R2_FB23_Pos (23U)
\r
5177 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
\r
5178 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
\r
5179 #define CAN_F8R2_FB24_Pos (24U)
\r
5180 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
\r
5181 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
\r
5182 #define CAN_F8R2_FB25_Pos (25U)
\r
5183 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
\r
5184 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
\r
5185 #define CAN_F8R2_FB26_Pos (26U)
\r
5186 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
\r
5187 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
\r
5188 #define CAN_F8R2_FB27_Pos (27U)
\r
5189 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
\r
5190 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
\r
5191 #define CAN_F8R2_FB28_Pos (28U)
\r
5192 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
\r
5193 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
\r
5194 #define CAN_F8R2_FB29_Pos (29U)
\r
5195 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
\r
5196 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
\r
5197 #define CAN_F8R2_FB30_Pos (30U)
\r
5198 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
\r
5199 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
\r
5200 #define CAN_F8R2_FB31_Pos (31U)
\r
5201 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
\r
5202 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
\r
5204 /******************* Bit definition for CAN_F9R2 register *******************/
\r
5205 #define CAN_F9R2_FB0_Pos (0U)
\r
5206 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
\r
5207 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
\r
5208 #define CAN_F9R2_FB1_Pos (1U)
\r
5209 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
\r
5210 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
\r
5211 #define CAN_F9R2_FB2_Pos (2U)
\r
5212 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
\r
5213 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
\r
5214 #define CAN_F9R2_FB3_Pos (3U)
\r
5215 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
\r
5216 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
\r
5217 #define CAN_F9R2_FB4_Pos (4U)
\r
5218 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
\r
5219 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
\r
5220 #define CAN_F9R2_FB5_Pos (5U)
\r
5221 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
\r
5222 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
\r
5223 #define CAN_F9R2_FB6_Pos (6U)
\r
5224 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
\r
5225 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
\r
5226 #define CAN_F9R2_FB7_Pos (7U)
\r
5227 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
\r
5228 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
\r
5229 #define CAN_F9R2_FB8_Pos (8U)
\r
5230 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
\r
5231 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
\r
5232 #define CAN_F9R2_FB9_Pos (9U)
\r
5233 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
\r
5234 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
\r
5235 #define CAN_F9R2_FB10_Pos (10U)
\r
5236 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
\r
5237 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
\r
5238 #define CAN_F9R2_FB11_Pos (11U)
\r
5239 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
\r
5240 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
\r
5241 #define CAN_F9R2_FB12_Pos (12U)
\r
5242 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
\r
5243 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
\r
5244 #define CAN_F9R2_FB13_Pos (13U)
\r
5245 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
\r
5246 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
\r
5247 #define CAN_F9R2_FB14_Pos (14U)
\r
5248 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
\r
5249 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
\r
5250 #define CAN_F9R2_FB15_Pos (15U)
\r
5251 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
\r
5252 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
\r
5253 #define CAN_F9R2_FB16_Pos (16U)
\r
5254 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
\r
5255 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
\r
5256 #define CAN_F9R2_FB17_Pos (17U)
\r
5257 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
\r
5258 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
\r
5259 #define CAN_F9R2_FB18_Pos (18U)
\r
5260 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
\r
5261 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
\r
5262 #define CAN_F9R2_FB19_Pos (19U)
\r
5263 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
\r
5264 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
\r
5265 #define CAN_F9R2_FB20_Pos (20U)
\r
5266 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
\r
5267 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
\r
5268 #define CAN_F9R2_FB21_Pos (21U)
\r
5269 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
\r
5270 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
\r
5271 #define CAN_F9R2_FB22_Pos (22U)
\r
5272 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
\r
5273 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
\r
5274 #define CAN_F9R2_FB23_Pos (23U)
\r
5275 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
\r
5276 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
\r
5277 #define CAN_F9R2_FB24_Pos (24U)
\r
5278 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
\r
5279 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
\r
5280 #define CAN_F9R2_FB25_Pos (25U)
\r
5281 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
\r
5282 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
\r
5283 #define CAN_F9R2_FB26_Pos (26U)
\r
5284 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
\r
5285 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
\r
5286 #define CAN_F9R2_FB27_Pos (27U)
\r
5287 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
\r
5288 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
\r
5289 #define CAN_F9R2_FB28_Pos (28U)
\r
5290 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
\r
5291 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
\r
5292 #define CAN_F9R2_FB29_Pos (29U)
\r
5293 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
\r
5294 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
\r
5295 #define CAN_F9R2_FB30_Pos (30U)
\r
5296 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
\r
5297 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
\r
5298 #define CAN_F9R2_FB31_Pos (31U)
\r
5299 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
\r
5300 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
\r
5302 /******************* Bit definition for CAN_F10R2 register ******************/
\r
5303 #define CAN_F10R2_FB0_Pos (0U)
\r
5304 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
\r
5305 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
\r
5306 #define CAN_F10R2_FB1_Pos (1U)
\r
5307 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
\r
5308 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
\r
5309 #define CAN_F10R2_FB2_Pos (2U)
\r
5310 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
\r
5311 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
\r
5312 #define CAN_F10R2_FB3_Pos (3U)
\r
5313 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
\r
5314 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
\r
5315 #define CAN_F10R2_FB4_Pos (4U)
\r
5316 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
\r
5317 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
\r
5318 #define CAN_F10R2_FB5_Pos (5U)
\r
5319 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
\r
5320 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
\r
5321 #define CAN_F10R2_FB6_Pos (6U)
\r
5322 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
\r
5323 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
\r
5324 #define CAN_F10R2_FB7_Pos (7U)
\r
5325 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
\r
5326 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
\r
5327 #define CAN_F10R2_FB8_Pos (8U)
\r
5328 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
\r
5329 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
\r
5330 #define CAN_F10R2_FB9_Pos (9U)
\r
5331 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
\r
5332 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
\r
5333 #define CAN_F10R2_FB10_Pos (10U)
\r
5334 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
\r
5335 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
\r
5336 #define CAN_F10R2_FB11_Pos (11U)
\r
5337 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
\r
5338 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
\r
5339 #define CAN_F10R2_FB12_Pos (12U)
\r
5340 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
\r
5341 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
\r
5342 #define CAN_F10R2_FB13_Pos (13U)
\r
5343 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
\r
5344 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
\r
5345 #define CAN_F10R2_FB14_Pos (14U)
\r
5346 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
\r
5347 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
\r
5348 #define CAN_F10R2_FB15_Pos (15U)
\r
5349 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
\r
5350 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
\r
5351 #define CAN_F10R2_FB16_Pos (16U)
\r
5352 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
\r
5353 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
\r
5354 #define CAN_F10R2_FB17_Pos (17U)
\r
5355 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
\r
5356 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
\r
5357 #define CAN_F10R2_FB18_Pos (18U)
\r
5358 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
\r
5359 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
\r
5360 #define CAN_F10R2_FB19_Pos (19U)
\r
5361 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
\r
5362 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
\r
5363 #define CAN_F10R2_FB20_Pos (20U)
\r
5364 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
\r
5365 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
\r
5366 #define CAN_F10R2_FB21_Pos (21U)
\r
5367 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
\r
5368 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
\r
5369 #define CAN_F10R2_FB22_Pos (22U)
\r
5370 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
\r
5371 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
\r
5372 #define CAN_F10R2_FB23_Pos (23U)
\r
5373 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
\r
5374 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
\r
5375 #define CAN_F10R2_FB24_Pos (24U)
\r
5376 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
\r
5377 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
\r
5378 #define CAN_F10R2_FB25_Pos (25U)
\r
5379 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
\r
5380 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
\r
5381 #define CAN_F10R2_FB26_Pos (26U)
\r
5382 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
\r
5383 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
\r
5384 #define CAN_F10R2_FB27_Pos (27U)
\r
5385 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
\r
5386 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
\r
5387 #define CAN_F10R2_FB28_Pos (28U)
\r
5388 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
\r
5389 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
\r
5390 #define CAN_F10R2_FB29_Pos (29U)
\r
5391 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
\r
5392 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
\r
5393 #define CAN_F10R2_FB30_Pos (30U)
\r
5394 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
\r
5395 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
\r
5396 #define CAN_F10R2_FB31_Pos (31U)
\r
5397 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
\r
5398 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
\r
5400 /******************* Bit definition for CAN_F11R2 register ******************/
\r
5401 #define CAN_F11R2_FB0_Pos (0U)
\r
5402 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
\r
5403 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
\r
5404 #define CAN_F11R2_FB1_Pos (1U)
\r
5405 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
\r
5406 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
\r
5407 #define CAN_F11R2_FB2_Pos (2U)
\r
5408 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
\r
5409 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
\r
5410 #define CAN_F11R2_FB3_Pos (3U)
\r
5411 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
\r
5412 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
\r
5413 #define CAN_F11R2_FB4_Pos (4U)
\r
5414 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
\r
5415 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
\r
5416 #define CAN_F11R2_FB5_Pos (5U)
\r
5417 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
\r
5418 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
\r
5419 #define CAN_F11R2_FB6_Pos (6U)
\r
5420 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
\r
5421 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
\r
5422 #define CAN_F11R2_FB7_Pos (7U)
\r
5423 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
\r
5424 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
\r
5425 #define CAN_F11R2_FB8_Pos (8U)
\r
5426 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
\r
5427 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
\r
5428 #define CAN_F11R2_FB9_Pos (9U)
\r
5429 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
\r
5430 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
\r
5431 #define CAN_F11R2_FB10_Pos (10U)
\r
5432 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
\r
5433 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
\r
5434 #define CAN_F11R2_FB11_Pos (11U)
\r
5435 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
\r
5436 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
\r
5437 #define CAN_F11R2_FB12_Pos (12U)
\r
5438 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
\r
5439 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
\r
5440 #define CAN_F11R2_FB13_Pos (13U)
\r
5441 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
\r
5442 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
\r
5443 #define CAN_F11R2_FB14_Pos (14U)
\r
5444 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
\r
5445 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
\r
5446 #define CAN_F11R2_FB15_Pos (15U)
\r
5447 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
\r
5448 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
\r
5449 #define CAN_F11R2_FB16_Pos (16U)
\r
5450 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
\r
5451 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
\r
5452 #define CAN_F11R2_FB17_Pos (17U)
\r
5453 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
\r
5454 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
\r
5455 #define CAN_F11R2_FB18_Pos (18U)
\r
5456 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
\r
5457 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
\r
5458 #define CAN_F11R2_FB19_Pos (19U)
\r
5459 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
\r
5460 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
\r
5461 #define CAN_F11R2_FB20_Pos (20U)
\r
5462 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
\r
5463 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
\r
5464 #define CAN_F11R2_FB21_Pos (21U)
\r
5465 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
\r
5466 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
\r
5467 #define CAN_F11R2_FB22_Pos (22U)
\r
5468 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
\r
5469 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
\r
5470 #define CAN_F11R2_FB23_Pos (23U)
\r
5471 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
\r
5472 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
\r
5473 #define CAN_F11R2_FB24_Pos (24U)
\r
5474 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
\r
5475 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
\r
5476 #define CAN_F11R2_FB25_Pos (25U)
\r
5477 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
\r
5478 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
\r
5479 #define CAN_F11R2_FB26_Pos (26U)
\r
5480 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
\r
5481 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
\r
5482 #define CAN_F11R2_FB27_Pos (27U)
\r
5483 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
\r
5484 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
\r
5485 #define CAN_F11R2_FB28_Pos (28U)
\r
5486 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
\r
5487 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
\r
5488 #define CAN_F11R2_FB29_Pos (29U)
\r
5489 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
\r
5490 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
\r
5491 #define CAN_F11R2_FB30_Pos (30U)
\r
5492 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
\r
5493 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
\r
5494 #define CAN_F11R2_FB31_Pos (31U)
\r
5495 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
\r
5496 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
\r
5498 /******************* Bit definition for CAN_F12R2 register ******************/
\r
5499 #define CAN_F12R2_FB0_Pos (0U)
\r
5500 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
\r
5501 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
\r
5502 #define CAN_F12R2_FB1_Pos (1U)
\r
5503 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
\r
5504 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
\r
5505 #define CAN_F12R2_FB2_Pos (2U)
\r
5506 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
\r
5507 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
\r
5508 #define CAN_F12R2_FB3_Pos (3U)
\r
5509 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
\r
5510 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
\r
5511 #define CAN_F12R2_FB4_Pos (4U)
\r
5512 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
\r
5513 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
\r
5514 #define CAN_F12R2_FB5_Pos (5U)
\r
5515 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
\r
5516 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
\r
5517 #define CAN_F12R2_FB6_Pos (6U)
\r
5518 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
\r
5519 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
\r
5520 #define CAN_F12R2_FB7_Pos (7U)
\r
5521 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
\r
5522 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
\r
5523 #define CAN_F12R2_FB8_Pos (8U)
\r
5524 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
\r
5525 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
\r
5526 #define CAN_F12R2_FB9_Pos (9U)
\r
5527 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
\r
5528 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
\r
5529 #define CAN_F12R2_FB10_Pos (10U)
\r
5530 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
\r
5531 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
\r
5532 #define CAN_F12R2_FB11_Pos (11U)
\r
5533 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
\r
5534 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
\r
5535 #define CAN_F12R2_FB12_Pos (12U)
\r
5536 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
\r
5537 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
\r
5538 #define CAN_F12R2_FB13_Pos (13U)
\r
5539 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
\r
5540 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
\r
5541 #define CAN_F12R2_FB14_Pos (14U)
\r
5542 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
\r
5543 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
\r
5544 #define CAN_F12R2_FB15_Pos (15U)
\r
5545 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
\r
5546 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
\r
5547 #define CAN_F12R2_FB16_Pos (16U)
\r
5548 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
\r
5549 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
\r
5550 #define CAN_F12R2_FB17_Pos (17U)
\r
5551 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
\r
5552 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
\r
5553 #define CAN_F12R2_FB18_Pos (18U)
\r
5554 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
\r
5555 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
\r
5556 #define CAN_F12R2_FB19_Pos (19U)
\r
5557 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
\r
5558 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
\r
5559 #define CAN_F12R2_FB20_Pos (20U)
\r
5560 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
\r
5561 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
\r
5562 #define CAN_F12R2_FB21_Pos (21U)
\r
5563 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
\r
5564 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
\r
5565 #define CAN_F12R2_FB22_Pos (22U)
\r
5566 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
\r
5567 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
\r
5568 #define CAN_F12R2_FB23_Pos (23U)
\r
5569 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
\r
5570 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
\r
5571 #define CAN_F12R2_FB24_Pos (24U)
\r
5572 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
\r
5573 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
\r
5574 #define CAN_F12R2_FB25_Pos (25U)
\r
5575 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
\r
5576 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
\r
5577 #define CAN_F12R2_FB26_Pos (26U)
\r
5578 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
\r
5579 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
\r
5580 #define CAN_F12R2_FB27_Pos (27U)
\r
5581 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
\r
5582 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
\r
5583 #define CAN_F12R2_FB28_Pos (28U)
\r
5584 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
\r
5585 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
\r
5586 #define CAN_F12R2_FB29_Pos (29U)
\r
5587 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
\r
5588 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
\r
5589 #define CAN_F12R2_FB30_Pos (30U)
\r
5590 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
\r
5591 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
\r
5592 #define CAN_F12R2_FB31_Pos (31U)
\r
5593 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
\r
5594 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
\r
5596 /******************* Bit definition for CAN_F13R2 register ******************/
\r
5597 #define CAN_F13R2_FB0_Pos (0U)
\r
5598 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
\r
5599 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
\r
5600 #define CAN_F13R2_FB1_Pos (1U)
\r
5601 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
\r
5602 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
\r
5603 #define CAN_F13R2_FB2_Pos (2U)
\r
5604 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
\r
5605 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
\r
5606 #define CAN_F13R2_FB3_Pos (3U)
\r
5607 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
\r
5608 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
\r
5609 #define CAN_F13R2_FB4_Pos (4U)
\r
5610 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
\r
5611 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
\r
5612 #define CAN_F13R2_FB5_Pos (5U)
\r
5613 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
\r
5614 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
\r
5615 #define CAN_F13R2_FB6_Pos (6U)
\r
5616 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
\r
5617 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
\r
5618 #define CAN_F13R2_FB7_Pos (7U)
\r
5619 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
\r
5620 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
\r
5621 #define CAN_F13R2_FB8_Pos (8U)
\r
5622 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
\r
5623 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
\r
5624 #define CAN_F13R2_FB9_Pos (9U)
\r
5625 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
\r
5626 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
\r
5627 #define CAN_F13R2_FB10_Pos (10U)
\r
5628 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
\r
5629 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
\r
5630 #define CAN_F13R2_FB11_Pos (11U)
\r
5631 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
\r
5632 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
\r
5633 #define CAN_F13R2_FB12_Pos (12U)
\r
5634 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
\r
5635 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
\r
5636 #define CAN_F13R2_FB13_Pos (13U)
\r
5637 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
\r
5638 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
\r
5639 #define CAN_F13R2_FB14_Pos (14U)
\r
5640 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
\r
5641 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
\r
5642 #define CAN_F13R2_FB15_Pos (15U)
\r
5643 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
\r
5644 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
\r
5645 #define CAN_F13R2_FB16_Pos (16U)
\r
5646 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
\r
5647 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
\r
5648 #define CAN_F13R2_FB17_Pos (17U)
\r
5649 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
\r
5650 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
\r
5651 #define CAN_F13R2_FB18_Pos (18U)
\r
5652 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
\r
5653 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
\r
5654 #define CAN_F13R2_FB19_Pos (19U)
\r
5655 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
\r
5656 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
\r
5657 #define CAN_F13R2_FB20_Pos (20U)
\r
5658 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
\r
5659 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
\r
5660 #define CAN_F13R2_FB21_Pos (21U)
\r
5661 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
\r
5662 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
\r
5663 #define CAN_F13R2_FB22_Pos (22U)
\r
5664 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
\r
5665 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
\r
5666 #define CAN_F13R2_FB23_Pos (23U)
\r
5667 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
\r
5668 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
\r
5669 #define CAN_F13R2_FB24_Pos (24U)
\r
5670 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
\r
5671 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
\r
5672 #define CAN_F13R2_FB25_Pos (25U)
\r
5673 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
\r
5674 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
\r
5675 #define CAN_F13R2_FB26_Pos (26U)
\r
5676 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
\r
5677 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
\r
5678 #define CAN_F13R2_FB27_Pos (27U)
\r
5679 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
\r
5680 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
\r
5681 #define CAN_F13R2_FB28_Pos (28U)
\r
5682 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
\r
5683 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
\r
5684 #define CAN_F13R2_FB29_Pos (29U)
\r
5685 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
\r
5686 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
\r
5687 #define CAN_F13R2_FB30_Pos (30U)
\r
5688 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
\r
5689 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
\r
5690 #define CAN_F13R2_FB31_Pos (31U)
\r
5691 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
\r
5692 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
\r
5694 /******************************************************************************/
\r
5696 /* HDMI-CEC (CEC) */
\r
5698 /******************************************************************************/
\r
5700 /******************* Bit definition for CEC_CR register *********************/
\r
5701 #define CEC_CR_CECEN_Pos (0U)
\r
5702 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
\r
5703 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
\r
5704 #define CEC_CR_TXSOM_Pos (1U)
\r
5705 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
\r
5706 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
\r
5707 #define CEC_CR_TXEOM_Pos (2U)
\r
5708 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
\r
5709 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
\r
5711 /******************* Bit definition for CEC_CFGR register *******************/
\r
5712 #define CEC_CFGR_SFT_Pos (0U)
\r
5713 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
\r
5714 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
\r
5715 #define CEC_CFGR_RXTOL_Pos (3U)
\r
5716 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
\r
5717 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
\r
5718 #define CEC_CFGR_BRESTP_Pos (4U)
\r
5719 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
\r
5720 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
\r
5721 #define CEC_CFGR_BREGEN_Pos (5U)
\r
5722 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
\r
5723 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
\r
5724 #define CEC_CFGR_LBPEGEN_Pos (6U)
\r
5725 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
\r
5726 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */
\r
5727 #define CEC_CFGR_BRDNOGEN_Pos (7U)
\r
5728 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
\r
5729 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */
\r
5730 #define CEC_CFGR_SFTOPT_Pos (8U)
\r
5731 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
\r
5732 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
\r
5733 #define CEC_CFGR_OAR_Pos (16U)
\r
5734 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
\r
5735 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
\r
5736 #define CEC_CFGR_LSTN_Pos (31U)
\r
5737 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
\r
5738 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
\r
5740 /******************* Bit definition for CEC_TXDR register *******************/
\r
5741 #define CEC_TXDR_TXD_Pos (0U)
\r
5742 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
\r
5743 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
\r
5745 /******************* Bit definition for CEC_RXDR register *******************/
\r
5746 #define CEC_RXDR_RXD_Pos (0U)
\r
5747 #define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
\r
5748 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
\r
5750 /******************* Bit definition for CEC_ISR register ********************/
\r
5751 #define CEC_ISR_RXBR_Pos (0U)
\r
5752 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
\r
5753 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
\r
5754 #define CEC_ISR_RXEND_Pos (1U)
\r
5755 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
\r
5756 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
\r
5757 #define CEC_ISR_RXOVR_Pos (2U)
\r
5758 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
\r
5759 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
\r
5760 #define CEC_ISR_BRE_Pos (3U)
\r
5761 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
\r
5762 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
\r
5763 #define CEC_ISR_SBPE_Pos (4U)
\r
5764 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
\r
5765 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
\r
5766 #define CEC_ISR_LBPE_Pos (5U)
\r
5767 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
\r
5768 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
\r
5769 #define CEC_ISR_RXACKE_Pos (6U)
\r
5770 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
\r
5771 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
\r
5772 #define CEC_ISR_ARBLST_Pos (7U)
\r
5773 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
\r
5774 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
\r
5775 #define CEC_ISR_TXBR_Pos (8U)
\r
5776 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
\r
5777 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
\r
5778 #define CEC_ISR_TXEND_Pos (9U)
\r
5779 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
\r
5780 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
\r
5781 #define CEC_ISR_TXUDR_Pos (10U)
\r
5782 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
\r
5783 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
\r
5784 #define CEC_ISR_TXERR_Pos (11U)
\r
5785 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
\r
5786 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
\r
5787 #define CEC_ISR_TXACKE_Pos (12U)
\r
5788 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
\r
5789 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
\r
5791 /******************* Bit definition for CEC_IER register ********************/
\r
5792 #define CEC_IER_RXBRIE_Pos (0U)
\r
5793 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
\r
5794 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
\r
5795 #define CEC_IER_RXENDIE_Pos (1U)
\r
5796 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
\r
5797 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
\r
5798 #define CEC_IER_RXOVRIE_Pos (2U)
\r
5799 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
\r
5800 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
\r
5801 #define CEC_IER_BREIE_Pos (3U)
\r
5802 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
\r
5803 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
\r
5804 #define CEC_IER_SBPEIE_Pos (4U)
\r
5805 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
\r
5806 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
\r
5807 #define CEC_IER_LBPEIE_Pos (5U)
\r
5808 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
\r
5809 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
\r
5810 #define CEC_IER_RXACKEIE_Pos (6U)
\r
5811 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
\r
5812 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
\r
5813 #define CEC_IER_ARBLSTIE_Pos (7U)
\r
5814 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
\r
5815 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
\r
5816 #define CEC_IER_TXBRIE_Pos (8U)
\r
5817 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
\r
5818 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
\r
5819 #define CEC_IER_TXENDIE_Pos (9U)
\r
5820 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
\r
5821 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
\r
5822 #define CEC_IER_TXUDRIE_Pos (10U)
\r
5823 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
\r
5824 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
\r
5825 #define CEC_IER_TXERRIE_Pos (11U)
\r
5826 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
\r
5827 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
\r
5828 #define CEC_IER_TXACKEIE_Pos (12U)
\r
5829 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
\r
5830 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
\r
5832 /******************************************************************************/
\r
5834 /* CRC calculation unit */
\r
5836 /******************************************************************************/
\r
5837 /******************* Bit definition for CRC_DR register *********************/
\r
5838 #define CRC_DR_DR_Pos (0U)
\r
5839 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
\r
5840 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
\r
5842 /******************* Bit definition for CRC_IDR register ********************/
\r
5843 #define CRC_IDR_IDR_Pos (0U)
\r
5844 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
\r
5845 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
\r
5847 /******************** Bit definition for CRC_CR register ********************/
\r
5848 #define CRC_CR_RESET_Pos (0U)
\r
5849 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
\r
5850 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
\r
5851 #define CRC_CR_POLYSIZE_Pos (3U)
\r
5852 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
\r
5853 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
\r
5854 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
\r
5855 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
\r
5856 #define CRC_CR_REV_IN_Pos (5U)
\r
5857 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
\r
5858 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
\r
5859 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
\r
5860 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
\r
5861 #define CRC_CR_REV_OUT_Pos (7U)
\r
5862 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
\r
5863 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
\r
5865 /******************* Bit definition for CRC_INIT register *******************/
\r
5866 #define CRC_INIT_INIT_Pos (0U)
\r
5867 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
\r
5868 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
\r
5870 /******************* Bit definition for CRC_POL register ********************/
\r
5871 #define CRC_POL_POL_Pos (0U)
\r
5872 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
\r
5873 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
\r
5876 /******************************************************************************/
\r
5878 /* Digital to Analog Converter */
\r
5880 /******************************************************************************/
\r
5881 /******************** Bit definition for DAC_CR register ********************/
\r
5882 #define DAC_CR_EN1_Pos (0U)
\r
5883 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
\r
5884 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
\r
5885 #define DAC_CR_BOFF1_Pos (1U)
\r
5886 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
\r
5887 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
\r
5888 #define DAC_CR_TEN1_Pos (2U)
\r
5889 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
\r
5890 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
\r
5891 #define DAC_CR_TSEL1_Pos (3U)
\r
5892 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
\r
5893 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
\r
5894 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
\r
5895 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
\r
5896 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
\r
5897 #define DAC_CR_WAVE1_Pos (6U)
\r
5898 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
\r
5899 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
\r
5900 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
\r
5901 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
\r
5902 #define DAC_CR_MAMP1_Pos (8U)
\r
5903 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
\r
5904 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
\r
5905 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
\r
5906 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
\r
5907 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
\r
5908 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
\r
5909 #define DAC_CR_DMAEN1_Pos (12U)
\r
5910 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
\r
5911 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
\r
5912 #define DAC_CR_DMAUDRIE1_Pos (13U)
\r
5913 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
\r
5914 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */
\r
5915 #define DAC_CR_EN2_Pos (16U)
\r
5916 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
\r
5917 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
\r
5918 #define DAC_CR_BOFF2_Pos (17U)
\r
5919 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
\r
5920 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
\r
5921 #define DAC_CR_TEN2_Pos (18U)
\r
5922 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
\r
5923 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
\r
5924 #define DAC_CR_TSEL2_Pos (19U)
\r
5925 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
\r
5926 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
\r
5927 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
\r
5928 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
\r
5929 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
\r
5930 #define DAC_CR_WAVE2_Pos (22U)
\r
5931 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
\r
5932 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
\r
5933 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
\r
5934 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
\r
5935 #define DAC_CR_MAMP2_Pos (24U)
\r
5936 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
\r
5937 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
\r
5938 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
\r
5939 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
\r
5940 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
\r
5941 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
\r
5942 #define DAC_CR_DMAEN2_Pos (28U)
\r
5943 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
\r
5944 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */
\r
5945 #define DAC_CR_DMAUDRIE2_Pos (29U)
\r
5946 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
\r
5947 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
\r
5949 /***************** Bit definition for DAC_SWTRIGR register ******************/
\r
5950 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
\r
5951 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
\r
5952 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
\r
5953 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
\r
5954 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
\r
5955 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
\r
5957 /***************** Bit definition for DAC_DHR12R1 register ******************/
\r
5958 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
\r
5959 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
\r
5960 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
\r
5962 /***************** Bit definition for DAC_DHR12L1 register ******************/
\r
5963 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
\r
5964 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
\r
5965 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
\r
5967 /****************** Bit definition for DAC_DHR8R1 register ******************/
\r
5968 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
\r
5969 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
\r
5970 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
\r
5972 /***************** Bit definition for DAC_DHR12R2 register ******************/
\r
5973 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
\r
5974 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
\r
5975 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
\r
5977 /***************** Bit definition for DAC_DHR12L2 register ******************/
\r
5978 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
\r
5979 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
\r
5980 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
\r
5982 /****************** Bit definition for DAC_DHR8R2 register ******************/
\r
5983 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
\r
5984 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
\r
5985 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
\r
5987 /***************** Bit definition for DAC_DHR12RD register ******************/
\r
5988 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
\r
5989 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
\r
5990 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
\r
5991 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
\r
5992 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
\r
5993 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
\r
5995 /***************** Bit definition for DAC_DHR12LD register ******************/
\r
5996 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
\r
5997 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
\r
5998 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
\r
5999 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
\r
6000 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
\r
6001 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
\r
6003 /****************** Bit definition for DAC_DHR8RD register ******************/
\r
6004 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
\r
6005 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
\r
6006 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
\r
6007 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
\r
6008 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
\r
6009 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
\r
6011 /******************* Bit definition for DAC_DOR1 register *******************/
\r
6012 #define DAC_DOR1_DACC1DOR_Pos (0U)
\r
6013 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
\r
6014 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
\r
6016 /******************* Bit definition for DAC_DOR2 register *******************/
\r
6017 #define DAC_DOR2_DACC2DOR_Pos (0U)
\r
6018 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
\r
6019 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
\r
6021 /******************** Bit definition for DAC_SR register ********************/
\r
6022 #define DAC_SR_DMAUDR1_Pos (13U)
\r
6023 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
\r
6024 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
\r
6025 #define DAC_SR_DMAUDR2_Pos (29U)
\r
6026 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
\r
6027 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
\r
6029 /******************************************************************************/
\r
6031 /* Digital Filter for Sigma Delta Modulators */
\r
6033 /******************************************************************************/
\r
6035 /**************** DFSDM channel configuration registers ********************/
\r
6037 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
\r
6038 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
\r
6039 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
\r
6040 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
\r
6041 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
\r
6042 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
\r
6043 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
\r
6044 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
\r
6045 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
\r
6046 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
\r
6047 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
\r
6048 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
\r
6049 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
\r
6050 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
\r
6051 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
\r
6052 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
\r
6053 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
\r
6054 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
\r
6055 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
\r
6056 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
\r
6057 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
\r
6058 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
\r
6059 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
\r
6060 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
\r
6061 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
\r
6062 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
\r
6063 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
\r
6064 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
\r
6065 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
\r
6066 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
\r
6067 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
\r
6068 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
\r
6069 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
\r
6070 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
\r
6071 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
\r
6072 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
\r
6073 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
\r
6074 #define DFSDM_CHCFGR1_SITP_Pos (0U)
\r
6075 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
\r
6076 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
\r
6077 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
\r
6078 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
\r
6080 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
\r
6081 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
\r
6082 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
\r
6083 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
\r
6084 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
\r
6085 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
\r
6086 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
\r
6088 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
\r
6089 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
\r
6090 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
\r
6091 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
\r
6092 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
\r
6093 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
\r
6094 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
\r
6095 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
\r
6096 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
\r
6097 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
\r
6098 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
\r
6099 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
\r
6100 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
\r
6101 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
\r
6102 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
\r
6104 /**************** Bit definition for DFSDM_CHWDATR register *******************/
\r
6105 #define DFSDM_CHWDATR_WDATA_Pos (0U)
\r
6106 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
\r
6107 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
\r
6109 /**************** Bit definition for DFSDM_CHDATINR register *****************/
\r
6110 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
\r
6111 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
\r
6112 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
\r
6113 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
\r
6114 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
\r
6115 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
\r
6117 /************************ DFSDM module registers ****************************/
\r
6119 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
\r
6120 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
\r
6121 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
\r
6122 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
\r
6123 #define DFSDM_FLTCR1_FAST_Pos (29U)
\r
6124 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
\r
6125 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
\r
6126 #define DFSDM_FLTCR1_RCH_Pos (24U)
\r
6127 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
\r
6128 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
\r
6129 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
\r
6130 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
\r
6131 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
\r
6132 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
\r
6133 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
\r
6134 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
\r
6135 #define DFSDM_FLTCR1_RCONT_Pos (18U)
\r
6136 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
\r
6137 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
\r
6138 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
\r
6139 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
\r
6140 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
\r
6141 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
\r
6142 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
\r
6143 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
\r
6144 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
\r
6145 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
\r
6146 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
\r
6147 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
\r
6148 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
\r
6149 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
\r
6150 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
\r
6151 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
\r
6152 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
\r
6153 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
\r
6154 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
\r
6155 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
\r
6156 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
\r
6157 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
\r
6158 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
\r
6159 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
\r
6160 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
\r
6161 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
\r
6162 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
\r
6163 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
\r
6164 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
\r
6165 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
\r
6166 #define DFSDM_FLTCR1_DFEN_Pos (0U)
\r
6167 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
\r
6168 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
\r
6170 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
\r
6171 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
\r
6172 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
\r
6173 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
\r
6174 #define DFSDM_FLTCR2_EXCH_Pos (8U)
\r
6175 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
\r
6176 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
\r
6177 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
\r
6178 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
\r
6179 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
\r
6180 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
\r
6181 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
\r
6182 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
\r
6183 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
\r
6184 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
\r
6185 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
\r
6186 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
\r
6187 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
\r
6188 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
\r
6189 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
\r
6190 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
\r
6191 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
\r
6192 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
\r
6193 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
\r
6194 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
\r
6195 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
\r
6196 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
\r
6197 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
\r
6199 /******************** Bit definition for DFSDM_FLTISR register *******************/
\r
6200 #define DFSDM_FLTISR_SCDF_Pos (24U)
\r
6201 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
\r
6202 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
\r
6203 #define DFSDM_FLTISR_CKABF_Pos (16U)
\r
6204 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
\r
6205 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
\r
6206 #define DFSDM_FLTISR_RCIP_Pos (14U)
\r
6207 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
\r
6208 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
\r
6209 #define DFSDM_FLTISR_JCIP_Pos (13U)
\r
6210 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
\r
6211 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
\r
6212 #define DFSDM_FLTISR_AWDF_Pos (4U)
\r
6213 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
\r
6214 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
\r
6215 #define DFSDM_FLTISR_ROVRF_Pos (3U)
\r
6216 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
\r
6217 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
\r
6218 #define DFSDM_FLTISR_JOVRF_Pos (2U)
\r
6219 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
\r
6220 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
\r
6221 #define DFSDM_FLTISR_REOCF_Pos (1U)
\r
6222 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
\r
6223 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
\r
6224 #define DFSDM_FLTISR_JEOCF_Pos (0U)
\r
6225 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
\r
6226 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
\r
6228 /******************** Bit definition for DFSDM_FLTICR register *******************/
\r
6229 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
\r
6230 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
\r
6231 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
\r
6232 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
\r
6233 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
\r
6234 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
\r
6235 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
\r
6236 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
\r
6237 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
\r
6238 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
\r
6239 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
\r
6240 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
\r
6242 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
\r
6243 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
\r
6244 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
\r
6245 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
\r
6247 /******************** Bit definition for DFSDM_FLTFCR register *******************/
\r
6248 #define DFSDM_FLTFCR_FORD_Pos (29U)
\r
6249 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
\r
6250 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
\r
6251 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
\r
6252 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
\r
6253 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
\r
6254 #define DFSDM_FLTFCR_FOSR_Pos (16U)
\r
6255 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
\r
6256 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
\r
6257 #define DFSDM_FLTFCR_IOSR_Pos (0U)
\r
6258 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
\r
6259 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
\r
6261 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
\r
6262 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
\r
6263 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
\r
6264 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
\r
6265 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
\r
6266 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
\r
6267 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
\r
6269 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
\r
6270 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
\r
6271 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
\r
6272 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
\r
6273 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
\r
6274 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
\r
6275 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
\r
6276 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
\r
6277 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
\r
6278 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
\r
6280 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
\r
6281 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
\r
6282 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
\r
6283 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
\r
6284 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
\r
6285 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
\r
6286 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
\r
6288 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
\r
6289 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
\r
6290 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
\r
6291 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
\r
6292 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
\r
6293 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
\r
6294 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
\r
6296 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
\r
6297 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
\r
6298 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
\r
6299 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
\r
6300 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
\r
6301 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
\r
6302 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
\r
6304 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
\r
6305 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
\r
6306 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
\r
6307 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
\r
6308 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
\r
6309 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
\r
6310 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
\r
6312 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
\r
6313 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
\r
6314 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
\r
6315 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
\r
6316 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
\r
6317 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
\r
6318 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
\r
6320 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
\r
6321 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
\r
6322 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
\r
6323 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
\r
6324 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
\r
6325 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
\r
6326 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
\r
6328 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
\r
6329 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
\r
6330 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
\r
6331 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
\r
6333 /* Legacy Defines */
\r
6334 #define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
\r
6335 #define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
\r
6336 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
\r
6338 /******************************************************************************/
\r
6342 /******************************************************************************/
\r
6344 /******************************************************************************/
\r
6348 /******************************************************************************/
\r
6349 /******************** Bits definition for DCMI_CR register ******************/
\r
6350 #define DCMI_CR_CAPTURE_Pos (0U)
\r
6351 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
\r
6352 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
\r
6353 #define DCMI_CR_CM_Pos (1U)
\r
6354 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
\r
6355 #define DCMI_CR_CM DCMI_CR_CM_Msk
\r
6356 #define DCMI_CR_CROP_Pos (2U)
\r
6357 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
\r
6358 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
\r
6359 #define DCMI_CR_JPEG_Pos (3U)
\r
6360 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
\r
6361 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
\r
6362 #define DCMI_CR_ESS_Pos (4U)
\r
6363 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
\r
6364 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
\r
6365 #define DCMI_CR_PCKPOL_Pos (5U)
\r
6366 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
\r
6367 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
\r
6368 #define DCMI_CR_HSPOL_Pos (6U)
\r
6369 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
\r
6370 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
\r
6371 #define DCMI_CR_VSPOL_Pos (7U)
\r
6372 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
\r
6373 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
\r
6374 #define DCMI_CR_FCRC_0 0x00000100U
\r
6375 #define DCMI_CR_FCRC_1 0x00000200U
\r
6376 #define DCMI_CR_EDM_0 0x00000400U
\r
6377 #define DCMI_CR_EDM_1 0x00000800U
\r
6378 #define DCMI_CR_CRE_Pos (12U)
\r
6379 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
\r
6380 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
\r
6381 #define DCMI_CR_ENABLE_Pos (14U)
\r
6382 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
\r
6383 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
\r
6384 #define DCMI_CR_BSM_Pos (16U)
\r
6385 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
\r
6386 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
\r
6387 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
\r
6388 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
\r
6389 #define DCMI_CR_OEBS_Pos (18U)
\r
6390 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
\r
6391 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
\r
6392 #define DCMI_CR_LSM_Pos (19U)
\r
6393 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
\r
6394 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
\r
6395 #define DCMI_CR_OELS_Pos (20U)
\r
6396 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
\r
6397 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
\r
6399 /******************** Bits definition for DCMI_SR register ******************/
\r
6400 #define DCMI_SR_HSYNC_Pos (0U)
\r
6401 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
\r
6402 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
\r
6403 #define DCMI_SR_VSYNC_Pos (1U)
\r
6404 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
\r
6405 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
\r
6406 #define DCMI_SR_FNE_Pos (2U)
\r
6407 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
\r
6408 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
\r
6410 /******************** Bits definition for DCMI_RIS register ****************/
\r
6411 #define DCMI_RIS_FRAME_RIS_Pos (0U)
\r
6412 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
\r
6413 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
\r
6414 #define DCMI_RIS_OVR_RIS_Pos (1U)
\r
6415 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
\r
6416 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
\r
6417 #define DCMI_RIS_ERR_RIS_Pos (2U)
\r
6418 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
\r
6419 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
\r
6420 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
\r
6421 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
\r
6422 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
\r
6423 #define DCMI_RIS_LINE_RIS_Pos (4U)
\r
6424 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
\r
6425 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
\r
6427 /* Legacy defines */
\r
6428 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
\r
6429 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
\r
6430 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
\r
6431 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
\r
6432 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
\r
6434 /******************** Bits definition for DCMI_IER register *****************/
\r
6435 #define DCMI_IER_FRAME_IE_Pos (0U)
\r
6436 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
\r
6437 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
\r
6438 #define DCMI_IER_OVR_IE_Pos (1U)
\r
6439 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
\r
6440 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
\r
6441 #define DCMI_IER_ERR_IE_Pos (2U)
\r
6442 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
\r
6443 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
\r
6444 #define DCMI_IER_VSYNC_IE_Pos (3U)
\r
6445 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
\r
6446 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
\r
6447 #define DCMI_IER_LINE_IE_Pos (4U)
\r
6448 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
\r
6449 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
\r
6452 /******************** Bits definition for DCMI_MIS register *****************/
\r
6453 #define DCMI_MIS_FRAME_MIS_Pos (0U)
\r
6454 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
\r
6455 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
\r
6456 #define DCMI_MIS_OVR_MIS_Pos (1U)
\r
6457 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
\r
6458 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
\r
6459 #define DCMI_MIS_ERR_MIS_Pos (2U)
\r
6460 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
\r
6461 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
\r
6462 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
\r
6463 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
\r
6464 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
\r
6465 #define DCMI_MIS_LINE_MIS_Pos (4U)
\r
6466 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
\r
6467 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
\r
6470 /******************** Bits definition for DCMI_ICR register *****************/
\r
6471 #define DCMI_ICR_FRAME_ISC_Pos (0U)
\r
6472 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
\r
6473 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
\r
6474 #define DCMI_ICR_OVR_ISC_Pos (1U)
\r
6475 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
\r
6476 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
\r
6477 #define DCMI_ICR_ERR_ISC_Pos (2U)
\r
6478 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
\r
6479 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
\r
6480 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
\r
6481 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
\r
6482 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
\r
6483 #define DCMI_ICR_LINE_ISC_Pos (4U)
\r
6484 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
\r
6485 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
\r
6488 /******************** Bits definition for DCMI_ESCR register ******************/
\r
6489 #define DCMI_ESCR_FSC_Pos (0U)
\r
6490 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
\r
6491 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
\r
6492 #define DCMI_ESCR_LSC_Pos (8U)
\r
6493 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
\r
6494 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
\r
6495 #define DCMI_ESCR_LEC_Pos (16U)
\r
6496 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
\r
6497 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
\r
6498 #define DCMI_ESCR_FEC_Pos (24U)
\r
6499 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
\r
6500 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
\r
6502 /******************** Bits definition for DCMI_ESUR register ******************/
\r
6503 #define DCMI_ESUR_FSU_Pos (0U)
\r
6504 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
\r
6505 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
\r
6506 #define DCMI_ESUR_LSU_Pos (8U)
\r
6507 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
\r
6508 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
\r
6509 #define DCMI_ESUR_LEU_Pos (16U)
\r
6510 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
\r
6511 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
\r
6512 #define DCMI_ESUR_FEU_Pos (24U)
\r
6513 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
\r
6514 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
\r
6516 /******************** Bits definition for DCMI_CWSTRT register ******************/
\r
6517 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
\r
6518 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
\r
6519 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
\r
6520 #define DCMI_CWSTRT_VST_Pos (16U)
\r
6521 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
\r
6522 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
\r
6524 /******************** Bits definition for DCMI_CWSIZE register ******************/
\r
6525 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
\r
6526 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
\r
6527 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
\r
6528 #define DCMI_CWSIZE_VLINE_Pos (16U)
\r
6529 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
\r
6530 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
\r
6532 /******************** Bits definition for DCMI_DR register ******************/
\r
6533 #define DCMI_DR_BYTE0_Pos (0U)
\r
6534 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
\r
6535 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
\r
6536 #define DCMI_DR_BYTE1_Pos (8U)
\r
6537 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
\r
6538 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
\r
6539 #define DCMI_DR_BYTE2_Pos (16U)
\r
6540 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
\r
6541 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
\r
6542 #define DCMI_DR_BYTE3_Pos (24U)
\r
6543 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
\r
6544 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
\r
6546 /******************************************************************************/
\r
6548 /* DMA Controller */
\r
6550 /******************************************************************************/
\r
6551 /******************** Bits definition for DMA_SxCR register *****************/
\r
6552 #define DMA_SxCR_CHSEL_Pos (25U)
\r
6553 #define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
\r
6554 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
\r
6555 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
\r
6556 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
\r
6557 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
\r
6558 #define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
\r
6559 #define DMA_SxCR_MBURST_Pos (23U)
\r
6560 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
\r
6561 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
\r
6562 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
\r
6563 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
\r
6564 #define DMA_SxCR_PBURST_Pos (21U)
\r
6565 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
\r
6566 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
\r
6567 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
\r
6568 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
\r
6569 #define DMA_SxCR_CT_Pos (19U)
\r
6570 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
\r
6571 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
\r
6572 #define DMA_SxCR_DBM_Pos (18U)
\r
6573 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
\r
6574 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
\r
6575 #define DMA_SxCR_PL_Pos (16U)
\r
6576 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
\r
6577 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
\r
6578 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
\r
6579 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
\r
6580 #define DMA_SxCR_PINCOS_Pos (15U)
\r
6581 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
\r
6582 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
\r
6583 #define DMA_SxCR_MSIZE_Pos (13U)
\r
6584 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
\r
6585 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
\r
6586 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
\r
6587 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
\r
6588 #define DMA_SxCR_PSIZE_Pos (11U)
\r
6589 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
\r
6590 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
\r
6591 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
\r
6592 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
\r
6593 #define DMA_SxCR_MINC_Pos (10U)
\r
6594 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
\r
6595 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
\r
6596 #define DMA_SxCR_PINC_Pos (9U)
\r
6597 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
\r
6598 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
\r
6599 #define DMA_SxCR_CIRC_Pos (8U)
\r
6600 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
\r
6601 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
\r
6602 #define DMA_SxCR_DIR_Pos (6U)
\r
6603 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
\r
6604 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
\r
6605 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
\r
6606 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
\r
6607 #define DMA_SxCR_PFCTRL_Pos (5U)
\r
6608 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
\r
6609 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
\r
6610 #define DMA_SxCR_TCIE_Pos (4U)
\r
6611 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
\r
6612 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
\r
6613 #define DMA_SxCR_HTIE_Pos (3U)
\r
6614 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
\r
6615 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
\r
6616 #define DMA_SxCR_TEIE_Pos (2U)
\r
6617 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
\r
6618 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
\r
6619 #define DMA_SxCR_DMEIE_Pos (1U)
\r
6620 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
\r
6621 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
\r
6622 #define DMA_SxCR_EN_Pos (0U)
\r
6623 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
\r
6624 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
\r
6626 /******************** Bits definition for DMA_SxCNDTR register **************/
\r
6627 #define DMA_SxNDT_Pos (0U)
\r
6628 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
\r
6629 #define DMA_SxNDT DMA_SxNDT_Msk
\r
6630 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
\r
6631 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
\r
6632 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
\r
6633 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
\r
6634 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
\r
6635 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
\r
6636 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
\r
6637 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
\r
6638 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
\r
6639 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
\r
6640 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
\r
6641 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
\r
6642 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
\r
6643 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
\r
6644 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
\r
6645 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
\r
6647 /******************** Bits definition for DMA_SxFCR register ****************/
\r
6648 #define DMA_SxFCR_FEIE_Pos (7U)
\r
6649 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
\r
6650 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
\r
6651 #define DMA_SxFCR_FS_Pos (3U)
\r
6652 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
\r
6653 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
\r
6654 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
\r
6655 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
\r
6656 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
\r
6657 #define DMA_SxFCR_DMDIS_Pos (2U)
\r
6658 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
\r
6659 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
\r
6660 #define DMA_SxFCR_FTH_Pos (0U)
\r
6661 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
\r
6662 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
\r
6663 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
\r
6664 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
\r
6666 /******************** Bits definition for DMA_LISR register *****************/
\r
6667 #define DMA_LISR_TCIF3_Pos (27U)
\r
6668 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
\r
6669 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
\r
6670 #define DMA_LISR_HTIF3_Pos (26U)
\r
6671 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
\r
6672 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
\r
6673 #define DMA_LISR_TEIF3_Pos (25U)
\r
6674 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
\r
6675 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
\r
6676 #define DMA_LISR_DMEIF3_Pos (24U)
\r
6677 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
\r
6678 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
\r
6679 #define DMA_LISR_FEIF3_Pos (22U)
\r
6680 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
\r
6681 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
\r
6682 #define DMA_LISR_TCIF2_Pos (21U)
\r
6683 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
\r
6684 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
\r
6685 #define DMA_LISR_HTIF2_Pos (20U)
\r
6686 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
\r
6687 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
\r
6688 #define DMA_LISR_TEIF2_Pos (19U)
\r
6689 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
\r
6690 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
\r
6691 #define DMA_LISR_DMEIF2_Pos (18U)
\r
6692 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
\r
6693 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
\r
6694 #define DMA_LISR_FEIF2_Pos (16U)
\r
6695 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
\r
6696 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
\r
6697 #define DMA_LISR_TCIF1_Pos (11U)
\r
6698 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
\r
6699 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
\r
6700 #define DMA_LISR_HTIF1_Pos (10U)
\r
6701 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
\r
6702 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
\r
6703 #define DMA_LISR_TEIF1_Pos (9U)
\r
6704 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
\r
6705 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
\r
6706 #define DMA_LISR_DMEIF1_Pos (8U)
\r
6707 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
\r
6708 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
\r
6709 #define DMA_LISR_FEIF1_Pos (6U)
\r
6710 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
\r
6711 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
\r
6712 #define DMA_LISR_TCIF0_Pos (5U)
\r
6713 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
\r
6714 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
\r
6715 #define DMA_LISR_HTIF0_Pos (4U)
\r
6716 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
\r
6717 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
\r
6718 #define DMA_LISR_TEIF0_Pos (3U)
\r
6719 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
\r
6720 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
\r
6721 #define DMA_LISR_DMEIF0_Pos (2U)
\r
6722 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
\r
6723 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
\r
6724 #define DMA_LISR_FEIF0_Pos (0U)
\r
6725 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
\r
6726 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
\r
6728 /******************** Bits definition for DMA_HISR register *****************/
\r
6729 #define DMA_HISR_TCIF7_Pos (27U)
\r
6730 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
\r
6731 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
\r
6732 #define DMA_HISR_HTIF7_Pos (26U)
\r
6733 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
\r
6734 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
\r
6735 #define DMA_HISR_TEIF7_Pos (25U)
\r
6736 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
\r
6737 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
\r
6738 #define DMA_HISR_DMEIF7_Pos (24U)
\r
6739 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
\r
6740 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
\r
6741 #define DMA_HISR_FEIF7_Pos (22U)
\r
6742 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
\r
6743 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
\r
6744 #define DMA_HISR_TCIF6_Pos (21U)
\r
6745 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
\r
6746 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
\r
6747 #define DMA_HISR_HTIF6_Pos (20U)
\r
6748 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
\r
6749 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
\r
6750 #define DMA_HISR_TEIF6_Pos (19U)
\r
6751 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
\r
6752 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
\r
6753 #define DMA_HISR_DMEIF6_Pos (18U)
\r
6754 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
\r
6755 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
\r
6756 #define DMA_HISR_FEIF6_Pos (16U)
\r
6757 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
\r
6758 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
\r
6759 #define DMA_HISR_TCIF5_Pos (11U)
\r
6760 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
\r
6761 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
\r
6762 #define DMA_HISR_HTIF5_Pos (10U)
\r
6763 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
\r
6764 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
\r
6765 #define DMA_HISR_TEIF5_Pos (9U)
\r
6766 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
\r
6767 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
\r
6768 #define DMA_HISR_DMEIF5_Pos (8U)
\r
6769 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
\r
6770 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
\r
6771 #define DMA_HISR_FEIF5_Pos (6U)
\r
6772 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
\r
6773 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
\r
6774 #define DMA_HISR_TCIF4_Pos (5U)
\r
6775 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
\r
6776 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
\r
6777 #define DMA_HISR_HTIF4_Pos (4U)
\r
6778 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
\r
6779 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
\r
6780 #define DMA_HISR_TEIF4_Pos (3U)
\r
6781 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
\r
6782 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
\r
6783 #define DMA_HISR_DMEIF4_Pos (2U)
\r
6784 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
\r
6785 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
\r
6786 #define DMA_HISR_FEIF4_Pos (0U)
\r
6787 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
\r
6788 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
\r
6790 /******************** Bits definition for DMA_LIFCR register ****************/
\r
6791 #define DMA_LIFCR_CTCIF3_Pos (27U)
\r
6792 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
\r
6793 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
\r
6794 #define DMA_LIFCR_CHTIF3_Pos (26U)
\r
6795 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
\r
6796 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
\r
6797 #define DMA_LIFCR_CTEIF3_Pos (25U)
\r
6798 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
\r
6799 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
\r
6800 #define DMA_LIFCR_CDMEIF3_Pos (24U)
\r
6801 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
\r
6802 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
\r
6803 #define DMA_LIFCR_CFEIF3_Pos (22U)
\r
6804 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
\r
6805 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
\r
6806 #define DMA_LIFCR_CTCIF2_Pos (21U)
\r
6807 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
\r
6808 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
\r
6809 #define DMA_LIFCR_CHTIF2_Pos (20U)
\r
6810 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
\r
6811 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
\r
6812 #define DMA_LIFCR_CTEIF2_Pos (19U)
\r
6813 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
\r
6814 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
\r
6815 #define DMA_LIFCR_CDMEIF2_Pos (18U)
\r
6816 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
\r
6817 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
\r
6818 #define DMA_LIFCR_CFEIF2_Pos (16U)
\r
6819 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
\r
6820 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
\r
6821 #define DMA_LIFCR_CTCIF1_Pos (11U)
\r
6822 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
\r
6823 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
\r
6824 #define DMA_LIFCR_CHTIF1_Pos (10U)
\r
6825 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
\r
6826 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
\r
6827 #define DMA_LIFCR_CTEIF1_Pos (9U)
\r
6828 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
\r
6829 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
\r
6830 #define DMA_LIFCR_CDMEIF1_Pos (8U)
\r
6831 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
\r
6832 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
\r
6833 #define DMA_LIFCR_CFEIF1_Pos (6U)
\r
6834 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
\r
6835 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
\r
6836 #define DMA_LIFCR_CTCIF0_Pos (5U)
\r
6837 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
\r
6838 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
\r
6839 #define DMA_LIFCR_CHTIF0_Pos (4U)
\r
6840 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
\r
6841 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
\r
6842 #define DMA_LIFCR_CTEIF0_Pos (3U)
\r
6843 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
\r
6844 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
\r
6845 #define DMA_LIFCR_CDMEIF0_Pos (2U)
\r
6846 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
\r
6847 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
\r
6848 #define DMA_LIFCR_CFEIF0_Pos (0U)
\r
6849 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
\r
6850 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
\r
6852 /******************** Bits definition for DMA_HIFCR register ****************/
\r
6853 #define DMA_HIFCR_CTCIF7_Pos (27U)
\r
6854 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
\r
6855 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
\r
6856 #define DMA_HIFCR_CHTIF7_Pos (26U)
\r
6857 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
\r
6858 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
\r
6859 #define DMA_HIFCR_CTEIF7_Pos (25U)
\r
6860 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
\r
6861 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
\r
6862 #define DMA_HIFCR_CDMEIF7_Pos (24U)
\r
6863 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
\r
6864 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
\r
6865 #define DMA_HIFCR_CFEIF7_Pos (22U)
\r
6866 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
\r
6867 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
\r
6868 #define DMA_HIFCR_CTCIF6_Pos (21U)
\r
6869 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
\r
6870 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
\r
6871 #define DMA_HIFCR_CHTIF6_Pos (20U)
\r
6872 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
\r
6873 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
\r
6874 #define DMA_HIFCR_CTEIF6_Pos (19U)
\r
6875 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
\r
6876 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
\r
6877 #define DMA_HIFCR_CDMEIF6_Pos (18U)
\r
6878 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
\r
6879 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
\r
6880 #define DMA_HIFCR_CFEIF6_Pos (16U)
\r
6881 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
\r
6882 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
\r
6883 #define DMA_HIFCR_CTCIF5_Pos (11U)
\r
6884 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
\r
6885 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
\r
6886 #define DMA_HIFCR_CHTIF5_Pos (10U)
\r
6887 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
\r
6888 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
\r
6889 #define DMA_HIFCR_CTEIF5_Pos (9U)
\r
6890 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
\r
6891 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
\r
6892 #define DMA_HIFCR_CDMEIF5_Pos (8U)
\r
6893 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
\r
6894 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
\r
6895 #define DMA_HIFCR_CFEIF5_Pos (6U)
\r
6896 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
\r
6897 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
\r
6898 #define DMA_HIFCR_CTCIF4_Pos (5U)
\r
6899 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
\r
6900 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
\r
6901 #define DMA_HIFCR_CHTIF4_Pos (4U)
\r
6902 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
\r
6903 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
\r
6904 #define DMA_HIFCR_CTEIF4_Pos (3U)
\r
6905 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
\r
6906 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
\r
6907 #define DMA_HIFCR_CDMEIF4_Pos (2U)
\r
6908 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
\r
6909 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
\r
6910 #define DMA_HIFCR_CFEIF4_Pos (0U)
\r
6911 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
\r
6912 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
\r
6914 /****************** Bit definition for DMA_SxPAR register ********************/
\r
6915 #define DMA_SxPAR_PA_Pos (0U)
\r
6916 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
\r
6917 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
\r
6919 /****************** Bit definition for DMA_SxM0AR register ********************/
\r
6920 #define DMA_SxM0AR_M0A_Pos (0U)
\r
6921 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
\r
6922 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
\r
6924 /****************** Bit definition for DMA_SxM1AR register ********************/
\r
6925 #define DMA_SxM1AR_M1A_Pos (0U)
\r
6926 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
\r
6927 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
\r
6929 /******************************************************************************/
\r
6931 /* AHB Master DMA2D Controller (DMA2D) */
\r
6933 /******************************************************************************/
\r
6935 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
\r
6937 #define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
\r
6938 /******************** Bit definition for DMA2D_CR register ******************/
\r
6940 #define DMA2D_CR_START_Pos (0U)
\r
6941 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
\r
6942 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
\r
6943 #define DMA2D_CR_SUSP_Pos (1U)
\r
6944 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
\r
6945 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
\r
6946 #define DMA2D_CR_ABORT_Pos (2U)
\r
6947 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
\r
6948 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
\r
6949 #define DMA2D_CR_TEIE_Pos (8U)
\r
6950 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
\r
6951 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
\r
6952 #define DMA2D_CR_TCIE_Pos (9U)
\r
6953 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
\r
6954 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
\r
6955 #define DMA2D_CR_TWIE_Pos (10U)
\r
6956 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
\r
6957 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
\r
6958 #define DMA2D_CR_CAEIE_Pos (11U)
\r
6959 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
\r
6960 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
\r
6961 #define DMA2D_CR_CTCIE_Pos (12U)
\r
6962 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
\r
6963 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
\r
6964 #define DMA2D_CR_CEIE_Pos (13U)
\r
6965 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
\r
6966 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
\r
6967 #define DMA2D_CR_MODE_Pos (16U)
\r
6968 #define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
\r
6969 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
\r
6970 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
\r
6971 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
\r
6973 /******************** Bit definition for DMA2D_ISR register *****************/
\r
6975 #define DMA2D_ISR_TEIF_Pos (0U)
\r
6976 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
\r
6977 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
\r
6978 #define DMA2D_ISR_TCIF_Pos (1U)
\r
6979 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
\r
6980 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
\r
6981 #define DMA2D_ISR_TWIF_Pos (2U)
\r
6982 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
\r
6983 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
\r
6984 #define DMA2D_ISR_CAEIF_Pos (3U)
\r
6985 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
\r
6986 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
\r
6987 #define DMA2D_ISR_CTCIF_Pos (4U)
\r
6988 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
\r
6989 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
\r
6990 #define DMA2D_ISR_CEIF_Pos (5U)
\r
6991 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
\r
6992 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
\r
6994 /******************** Bit definition for DMA2D_IFCR register ****************/
\r
6996 #define DMA2D_IFCR_CTEIF_Pos (0U)
\r
6997 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
\r
6998 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
\r
6999 #define DMA2D_IFCR_CTCIF_Pos (1U)
\r
7000 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
\r
7001 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
\r
7002 #define DMA2D_IFCR_CTWIF_Pos (2U)
\r
7003 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
\r
7004 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
\r
7005 #define DMA2D_IFCR_CAECIF_Pos (3U)
\r
7006 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
\r
7007 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
\r
7008 #define DMA2D_IFCR_CCTCIF_Pos (4U)
\r
7009 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
\r
7010 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
\r
7011 #define DMA2D_IFCR_CCEIF_Pos (5U)
\r
7012 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
\r
7013 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
\r
7015 /* Legacy defines */
\r
7016 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
\r
7017 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
\r
7018 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
\r
7019 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
\r
7020 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
\r
7021 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
\r
7023 /******************** Bit definition for DMA2D_FGMAR register ***************/
\r
7025 #define DMA2D_FGMAR_MA_Pos (0U)
\r
7026 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
7027 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
\r
7029 /******************** Bit definition for DMA2D_FGOR register ****************/
\r
7031 #define DMA2D_FGOR_LO_Pos (0U)
\r
7032 #define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
\r
7033 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
\r
7035 /******************** Bit definition for DMA2D_BGMAR register ***************/
\r
7037 #define DMA2D_BGMAR_MA_Pos (0U)
\r
7038 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
7039 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
\r
7041 /******************** Bit definition for DMA2D_BGOR register ****************/
\r
7043 #define DMA2D_BGOR_LO_Pos (0U)
\r
7044 #define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
\r
7045 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
\r
7047 /******************** Bit definition for DMA2D_FGPFCCR register *************/
\r
7049 #define DMA2D_FGPFCCR_CM_Pos (0U)
\r
7050 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
\r
7051 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
\r
7052 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
\r
7053 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
\r
7054 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
\r
7055 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
\r
7056 #define DMA2D_FGPFCCR_CCM_Pos (4U)
\r
7057 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
\r
7058 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
\r
7059 #define DMA2D_FGPFCCR_START_Pos (5U)
\r
7060 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
\r
7061 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
\r
7062 #define DMA2D_FGPFCCR_CS_Pos (8U)
\r
7063 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
\r
7064 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
\r
7065 #define DMA2D_FGPFCCR_AM_Pos (16U)
\r
7066 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
\r
7067 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
\r
7068 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
\r
7069 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
\r
7070 #define DMA2D_FGPFCCR_AI_Pos (20U)
\r
7071 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
\r
7072 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
\r
7073 #define DMA2D_FGPFCCR_RBS_Pos (21U)
\r
7074 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
\r
7075 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
\r
7076 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
\r
7077 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
\r
7078 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
\r
7080 /******************** Bit definition for DMA2D_FGCOLR register **************/
\r
7082 #define DMA2D_FGCOLR_BLUE_Pos (0U)
\r
7083 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
\r
7084 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
\r
7085 #define DMA2D_FGCOLR_GREEN_Pos (8U)
\r
7086 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
\r
7087 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
\r
7088 #define DMA2D_FGCOLR_RED_Pos (16U)
\r
7089 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
\r
7090 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
\r
7092 /******************** Bit definition for DMA2D_BGPFCCR register *************/
\r
7094 #define DMA2D_BGPFCCR_CM_Pos (0U)
\r
7095 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
\r
7096 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
\r
7097 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
\r
7098 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
\r
7099 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
\r
7100 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
\r
7101 #define DMA2D_BGPFCCR_CCM_Pos (4U)
\r
7102 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
\r
7103 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
\r
7104 #define DMA2D_BGPFCCR_START_Pos (5U)
\r
7105 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
\r
7106 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
\r
7107 #define DMA2D_BGPFCCR_CS_Pos (8U)
\r
7108 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
\r
7109 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
\r
7110 #define DMA2D_BGPFCCR_AM_Pos (16U)
\r
7111 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
\r
7112 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
\r
7113 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
\r
7114 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
\r
7115 #define DMA2D_BGPFCCR_AI_Pos (20U)
\r
7116 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
\r
7117 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
\r
7118 #define DMA2D_BGPFCCR_RBS_Pos (21U)
\r
7119 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
\r
7120 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
\r
7121 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
\r
7122 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
\r
7123 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
\r
7125 /******************** Bit definition for DMA2D_BGCOLR register **************/
\r
7127 #define DMA2D_BGCOLR_BLUE_Pos (0U)
\r
7128 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
\r
7129 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
\r
7130 #define DMA2D_BGCOLR_GREEN_Pos (8U)
\r
7131 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
\r
7132 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
\r
7133 #define DMA2D_BGCOLR_RED_Pos (16U)
\r
7134 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
\r
7135 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
\r
7137 /******************** Bit definition for DMA2D_FGCMAR register **************/
\r
7139 #define DMA2D_FGCMAR_MA_Pos (0U)
\r
7140 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
7141 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
\r
7143 /******************** Bit definition for DMA2D_BGCMAR register **************/
\r
7145 #define DMA2D_BGCMAR_MA_Pos (0U)
\r
7146 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
7147 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
\r
7149 /******************** Bit definition for DMA2D_OPFCCR register **************/
\r
7151 #define DMA2D_OPFCCR_CM_Pos (0U)
\r
7152 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
\r
7153 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
\r
7154 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
\r
7155 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
\r
7156 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
\r
7157 #define DMA2D_OPFCCR_AI_Pos (20U)
\r
7158 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
\r
7159 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
\r
7160 #define DMA2D_OPFCCR_RBS_Pos (21U)
\r
7161 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
\r
7162 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
\r
7164 /******************** Bit definition for DMA2D_OCOLR register ***************/
\r
7166 /*!<Mode_ARGB8888/RGB888 */
\r
7168 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
\r
7169 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
\r
7170 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
\r
7171 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
\r
7173 /*!<Mode_RGB565 */
\r
7174 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
\r
7175 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
\r
7176 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
\r
7178 /*!<Mode_ARGB1555 */
\r
7179 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
\r
7180 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
\r
7181 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
\r
7182 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
\r
7184 /*!<Mode_ARGB4444 */
\r
7185 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
\r
7186 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
\r
7187 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
\r
7188 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
\r
7190 /******************** Bit definition for DMA2D_OMAR register ****************/
\r
7192 #define DMA2D_OMAR_MA_Pos (0U)
\r
7193 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
7194 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
\r
7196 /******************** Bit definition for DMA2D_OOR register *****************/
\r
7198 #define DMA2D_OOR_LO_Pos (0U)
\r
7199 #define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
\r
7200 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
\r
7202 /******************** Bit definition for DMA2D_NLR register *****************/
\r
7204 #define DMA2D_NLR_NL_Pos (0U)
\r
7205 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
\r
7206 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
\r
7207 #define DMA2D_NLR_PL_Pos (16U)
\r
7208 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
\r
7209 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
\r
7211 /******************** Bit definition for DMA2D_LWR register *****************/
\r
7213 #define DMA2D_LWR_LW_Pos (0U)
\r
7214 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
\r
7215 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
\r
7217 /******************** Bit definition for DMA2D_AMTCR register ***************/
\r
7219 #define DMA2D_AMTCR_EN_Pos (0U)
\r
7220 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
\r
7221 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
\r
7222 #define DMA2D_AMTCR_DT_Pos (8U)
\r
7223 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
\r
7224 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
\r
7227 /******************** Bit definition for DMA2D_FGCLUT register **************/
\r
7229 /******************** Bit definition for DMA2D_BGCLUT register **************/
\r
7231 /******************************************************************************/
\r
7233 /* External Interrupt/Event Controller */
\r
7235 /******************************************************************************/
\r
7236 /******************* Bit definition for EXTI_IMR register *******************/
\r
7237 #define EXTI_IMR_MR0_Pos (0U)
\r
7238 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
\r
7239 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
\r
7240 #define EXTI_IMR_MR1_Pos (1U)
\r
7241 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
\r
7242 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
\r
7243 #define EXTI_IMR_MR2_Pos (2U)
\r
7244 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
\r
7245 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
\r
7246 #define EXTI_IMR_MR3_Pos (3U)
\r
7247 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
\r
7248 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
\r
7249 #define EXTI_IMR_MR4_Pos (4U)
\r
7250 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
\r
7251 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
\r
7252 #define EXTI_IMR_MR5_Pos (5U)
\r
7253 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
\r
7254 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
\r
7255 #define EXTI_IMR_MR6_Pos (6U)
\r
7256 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
\r
7257 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
\r
7258 #define EXTI_IMR_MR7_Pos (7U)
\r
7259 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
\r
7260 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
\r
7261 #define EXTI_IMR_MR8_Pos (8U)
\r
7262 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
\r
7263 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
\r
7264 #define EXTI_IMR_MR9_Pos (9U)
\r
7265 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
\r
7266 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
\r
7267 #define EXTI_IMR_MR10_Pos (10U)
\r
7268 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
\r
7269 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
\r
7270 #define EXTI_IMR_MR11_Pos (11U)
\r
7271 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
\r
7272 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
\r
7273 #define EXTI_IMR_MR12_Pos (12U)
\r
7274 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
\r
7275 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
\r
7276 #define EXTI_IMR_MR13_Pos (13U)
\r
7277 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
\r
7278 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
\r
7279 #define EXTI_IMR_MR14_Pos (14U)
\r
7280 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
\r
7281 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
\r
7282 #define EXTI_IMR_MR15_Pos (15U)
\r
7283 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
\r
7284 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
\r
7285 #define EXTI_IMR_MR16_Pos (16U)
\r
7286 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
\r
7287 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
\r
7288 #define EXTI_IMR_MR17_Pos (17U)
\r
7289 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
\r
7290 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
\r
7291 #define EXTI_IMR_MR18_Pos (18U)
\r
7292 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
\r
7293 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
\r
7294 #define EXTI_IMR_MR19_Pos (19U)
\r
7295 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
\r
7296 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
\r
7297 #define EXTI_IMR_MR20_Pos (20U)
\r
7298 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
\r
7299 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
\r
7300 #define EXTI_IMR_MR21_Pos (21U)
\r
7301 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
\r
7302 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
\r
7303 #define EXTI_IMR_MR22_Pos (22U)
\r
7304 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
\r
7305 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
\r
7306 #define EXTI_IMR_MR23_Pos (23U)
\r
7307 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
\r
7308 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
\r
7309 #define EXTI_IMR_MR24_Pos (24U)
\r
7310 #define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
\r
7311 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
\r
7313 /* Reference Defines */
\r
7314 #define EXTI_IMR_IM0 EXTI_IMR_MR0
\r
7315 #define EXTI_IMR_IM1 EXTI_IMR_MR1
\r
7316 #define EXTI_IMR_IM2 EXTI_IMR_MR2
\r
7317 #define EXTI_IMR_IM3 EXTI_IMR_MR3
\r
7318 #define EXTI_IMR_IM4 EXTI_IMR_MR4
\r
7319 #define EXTI_IMR_IM5 EXTI_IMR_MR5
\r
7320 #define EXTI_IMR_IM6 EXTI_IMR_MR6
\r
7321 #define EXTI_IMR_IM7 EXTI_IMR_MR7
\r
7322 #define EXTI_IMR_IM8 EXTI_IMR_MR8
\r
7323 #define EXTI_IMR_IM9 EXTI_IMR_MR9
\r
7324 #define EXTI_IMR_IM10 EXTI_IMR_MR10
\r
7325 #define EXTI_IMR_IM11 EXTI_IMR_MR11
\r
7326 #define EXTI_IMR_IM12 EXTI_IMR_MR12
\r
7327 #define EXTI_IMR_IM13 EXTI_IMR_MR13
\r
7328 #define EXTI_IMR_IM14 EXTI_IMR_MR14
\r
7329 #define EXTI_IMR_IM15 EXTI_IMR_MR15
\r
7330 #define EXTI_IMR_IM16 EXTI_IMR_MR16
\r
7331 #define EXTI_IMR_IM17 EXTI_IMR_MR17
\r
7332 #define EXTI_IMR_IM18 EXTI_IMR_MR18
\r
7333 #define EXTI_IMR_IM19 EXTI_IMR_MR19
\r
7334 #define EXTI_IMR_IM20 EXTI_IMR_MR20
\r
7335 #define EXTI_IMR_IM21 EXTI_IMR_MR21
\r
7336 #define EXTI_IMR_IM22 EXTI_IMR_MR22
\r
7337 #define EXTI_IMR_IM23 EXTI_IMR_MR23
\r
7338 #define EXTI_IMR_IM24 EXTI_IMR_MR24
\r
7340 #define EXTI_IMR_IM_Pos (0U)
\r
7341 #define EXTI_IMR_IM_Msk (0x1FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x01FFFFFF */
\r
7342 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
\r
7344 /******************* Bit definition for EXTI_EMR register *******************/
\r
7345 #define EXTI_EMR_MR0_Pos (0U)
\r
7346 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
\r
7347 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
\r
7348 #define EXTI_EMR_MR1_Pos (1U)
\r
7349 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
\r
7350 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
\r
7351 #define EXTI_EMR_MR2_Pos (2U)
\r
7352 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
\r
7353 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
\r
7354 #define EXTI_EMR_MR3_Pos (3U)
\r
7355 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
\r
7356 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
\r
7357 #define EXTI_EMR_MR4_Pos (4U)
\r
7358 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
\r
7359 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
\r
7360 #define EXTI_EMR_MR5_Pos (5U)
\r
7361 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
\r
7362 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
\r
7363 #define EXTI_EMR_MR6_Pos (6U)
\r
7364 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
\r
7365 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
\r
7366 #define EXTI_EMR_MR7_Pos (7U)
\r
7367 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
\r
7368 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
\r
7369 #define EXTI_EMR_MR8_Pos (8U)
\r
7370 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
\r
7371 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
\r
7372 #define EXTI_EMR_MR9_Pos (9U)
\r
7373 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
\r
7374 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
\r
7375 #define EXTI_EMR_MR10_Pos (10U)
\r
7376 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
\r
7377 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
\r
7378 #define EXTI_EMR_MR11_Pos (11U)
\r
7379 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
\r
7380 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
\r
7381 #define EXTI_EMR_MR12_Pos (12U)
\r
7382 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
\r
7383 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
\r
7384 #define EXTI_EMR_MR13_Pos (13U)
\r
7385 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
\r
7386 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
\r
7387 #define EXTI_EMR_MR14_Pos (14U)
\r
7388 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
\r
7389 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
\r
7390 #define EXTI_EMR_MR15_Pos (15U)
\r
7391 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
\r
7392 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
\r
7393 #define EXTI_EMR_MR16_Pos (16U)
\r
7394 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
\r
7395 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
\r
7396 #define EXTI_EMR_MR17_Pos (17U)
\r
7397 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
\r
7398 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
\r
7399 #define EXTI_EMR_MR18_Pos (18U)
\r
7400 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
\r
7401 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
\r
7402 #define EXTI_EMR_MR19_Pos (19U)
\r
7403 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
\r
7404 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
\r
7405 #define EXTI_EMR_MR20_Pos (20U)
\r
7406 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
\r
7407 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
\r
7408 #define EXTI_EMR_MR21_Pos (21U)
\r
7409 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
\r
7410 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
\r
7411 #define EXTI_EMR_MR22_Pos (22U)
\r
7412 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
\r
7413 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
\r
7414 #define EXTI_EMR_MR23_Pos (23U)
\r
7415 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
\r
7416 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
\r
7417 #define EXTI_EMR_MR24_Pos (24U)
\r
7418 #define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
\r
7419 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
\r
7421 /* Reference Defines */
\r
7422 #define EXTI_EMR_EM0 EXTI_EMR_MR0
\r
7423 #define EXTI_EMR_EM1 EXTI_EMR_MR1
\r
7424 #define EXTI_EMR_EM2 EXTI_EMR_MR2
\r
7425 #define EXTI_EMR_EM3 EXTI_EMR_MR3
\r
7426 #define EXTI_EMR_EM4 EXTI_EMR_MR4
\r
7427 #define EXTI_EMR_EM5 EXTI_EMR_MR5
\r
7428 #define EXTI_EMR_EM6 EXTI_EMR_MR6
\r
7429 #define EXTI_EMR_EM7 EXTI_EMR_MR7
\r
7430 #define EXTI_EMR_EM8 EXTI_EMR_MR8
\r
7431 #define EXTI_EMR_EM9 EXTI_EMR_MR9
\r
7432 #define EXTI_EMR_EM10 EXTI_EMR_MR10
\r
7433 #define EXTI_EMR_EM11 EXTI_EMR_MR11
\r
7434 #define EXTI_EMR_EM12 EXTI_EMR_MR12
\r
7435 #define EXTI_EMR_EM13 EXTI_EMR_MR13
\r
7436 #define EXTI_EMR_EM14 EXTI_EMR_MR14
\r
7437 #define EXTI_EMR_EM15 EXTI_EMR_MR15
\r
7438 #define EXTI_EMR_EM16 EXTI_EMR_MR16
\r
7439 #define EXTI_EMR_EM17 EXTI_EMR_MR17
\r
7440 #define EXTI_EMR_EM18 EXTI_EMR_MR18
\r
7441 #define EXTI_EMR_EM19 EXTI_EMR_MR19
\r
7442 #define EXTI_EMR_EM20 EXTI_EMR_MR20
\r
7443 #define EXTI_EMR_EM21 EXTI_EMR_MR21
\r
7444 #define EXTI_EMR_EM22 EXTI_EMR_MR22
\r
7445 #define EXTI_EMR_EM23 EXTI_EMR_MR23
\r
7446 #define EXTI_EMR_EM24 EXTI_EMR_MR24
\r
7449 /****************** Bit definition for EXTI_RTSR register *******************/
\r
7450 #define EXTI_RTSR_TR0_Pos (0U)
\r
7451 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
\r
7452 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
\r
7453 #define EXTI_RTSR_TR1_Pos (1U)
\r
7454 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
\r
7455 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
\r
7456 #define EXTI_RTSR_TR2_Pos (2U)
\r
7457 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
\r
7458 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
\r
7459 #define EXTI_RTSR_TR3_Pos (3U)
\r
7460 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
\r
7461 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
\r
7462 #define EXTI_RTSR_TR4_Pos (4U)
\r
7463 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
\r
7464 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
\r
7465 #define EXTI_RTSR_TR5_Pos (5U)
\r
7466 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
\r
7467 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
\r
7468 #define EXTI_RTSR_TR6_Pos (6U)
\r
7469 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
\r
7470 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
\r
7471 #define EXTI_RTSR_TR7_Pos (7U)
\r
7472 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
\r
7473 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
\r
7474 #define EXTI_RTSR_TR8_Pos (8U)
\r
7475 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
\r
7476 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
\r
7477 #define EXTI_RTSR_TR9_Pos (9U)
\r
7478 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
\r
7479 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
\r
7480 #define EXTI_RTSR_TR10_Pos (10U)
\r
7481 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
\r
7482 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
\r
7483 #define EXTI_RTSR_TR11_Pos (11U)
\r
7484 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
\r
7485 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
\r
7486 #define EXTI_RTSR_TR12_Pos (12U)
\r
7487 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
\r
7488 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
\r
7489 #define EXTI_RTSR_TR13_Pos (13U)
\r
7490 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
\r
7491 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
\r
7492 #define EXTI_RTSR_TR14_Pos (14U)
\r
7493 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
\r
7494 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
\r
7495 #define EXTI_RTSR_TR15_Pos (15U)
\r
7496 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
\r
7497 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
\r
7498 #define EXTI_RTSR_TR16_Pos (16U)
\r
7499 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
\r
7500 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
\r
7501 #define EXTI_RTSR_TR17_Pos (17U)
\r
7502 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
\r
7503 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
\r
7504 #define EXTI_RTSR_TR18_Pos (18U)
\r
7505 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
\r
7506 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
\r
7507 #define EXTI_RTSR_TR19_Pos (19U)
\r
7508 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
\r
7509 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
\r
7510 #define EXTI_RTSR_TR20_Pos (20U)
\r
7511 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
\r
7512 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
\r
7513 #define EXTI_RTSR_TR21_Pos (21U)
\r
7514 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
\r
7515 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
\r
7516 #define EXTI_RTSR_TR22_Pos (22U)
\r
7517 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
\r
7518 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
\r
7519 #define EXTI_RTSR_TR23_Pos (23U)
\r
7520 #define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
\r
7521 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
\r
7522 #define EXTI_RTSR_TR24_Pos (24U)
\r
7523 #define EXTI_RTSR_TR24_Msk (0x1UL << EXTI_RTSR_TR24_Pos) /*!< 0x01000000 */
\r
7524 #define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk /*!< Rising trigger event configuration bit of line 24 */
\r
7526 /****************** Bit definition for EXTI_FTSR register *******************/
\r
7527 #define EXTI_FTSR_TR0_Pos (0U)
\r
7528 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
\r
7529 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
\r
7530 #define EXTI_FTSR_TR1_Pos (1U)
\r
7531 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
\r
7532 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
\r
7533 #define EXTI_FTSR_TR2_Pos (2U)
\r
7534 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
\r
7535 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
\r
7536 #define EXTI_FTSR_TR3_Pos (3U)
\r
7537 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
\r
7538 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
\r
7539 #define EXTI_FTSR_TR4_Pos (4U)
\r
7540 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
\r
7541 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
\r
7542 #define EXTI_FTSR_TR5_Pos (5U)
\r
7543 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
\r
7544 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
\r
7545 #define EXTI_FTSR_TR6_Pos (6U)
\r
7546 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
\r
7547 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
\r
7548 #define EXTI_FTSR_TR7_Pos (7U)
\r
7549 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
\r
7550 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
\r
7551 #define EXTI_FTSR_TR8_Pos (8U)
\r
7552 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
\r
7553 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
\r
7554 #define EXTI_FTSR_TR9_Pos (9U)
\r
7555 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
\r
7556 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
\r
7557 #define EXTI_FTSR_TR10_Pos (10U)
\r
7558 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
\r
7559 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
\r
7560 #define EXTI_FTSR_TR11_Pos (11U)
\r
7561 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
\r
7562 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
\r
7563 #define EXTI_FTSR_TR12_Pos (12U)
\r
7564 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
\r
7565 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
\r
7566 #define EXTI_FTSR_TR13_Pos (13U)
\r
7567 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
\r
7568 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
\r
7569 #define EXTI_FTSR_TR14_Pos (14U)
\r
7570 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
\r
7571 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
\r
7572 #define EXTI_FTSR_TR15_Pos (15U)
\r
7573 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
\r
7574 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
\r
7575 #define EXTI_FTSR_TR16_Pos (16U)
\r
7576 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
\r
7577 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
\r
7578 #define EXTI_FTSR_TR17_Pos (17U)
\r
7579 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
\r
7580 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
\r
7581 #define EXTI_FTSR_TR18_Pos (18U)
\r
7582 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
\r
7583 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
\r
7584 #define EXTI_FTSR_TR19_Pos (19U)
\r
7585 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
\r
7586 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
\r
7587 #define EXTI_FTSR_TR20_Pos (20U)
\r
7588 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
\r
7589 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
\r
7590 #define EXTI_FTSR_TR21_Pos (21U)
\r
7591 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
\r
7592 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
\r
7593 #define EXTI_FTSR_TR22_Pos (22U)
\r
7594 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
\r
7595 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
\r
7596 #define EXTI_FTSR_TR23_Pos (23U)
\r
7597 #define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
\r
7598 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
\r
7599 #define EXTI_FTSR_TR24_Pos (24U)
\r
7600 #define EXTI_FTSR_TR24_Msk (0x1UL << EXTI_FTSR_TR24_Pos) /*!< 0x01000000 */
\r
7601 #define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk /*!< Falling trigger event configuration bit of line 24 */
\r
7603 /****************** Bit definition for EXTI_SWIER register ******************/
\r
7604 #define EXTI_SWIER_SWIER0_Pos (0U)
\r
7605 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
\r
7606 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
\r
7607 #define EXTI_SWIER_SWIER1_Pos (1U)
\r
7608 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
\r
7609 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
\r
7610 #define EXTI_SWIER_SWIER2_Pos (2U)
\r
7611 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
\r
7612 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
\r
7613 #define EXTI_SWIER_SWIER3_Pos (3U)
\r
7614 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
\r
7615 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
\r
7616 #define EXTI_SWIER_SWIER4_Pos (4U)
\r
7617 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
\r
7618 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
\r
7619 #define EXTI_SWIER_SWIER5_Pos (5U)
\r
7620 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
\r
7621 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
\r
7622 #define EXTI_SWIER_SWIER6_Pos (6U)
\r
7623 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
\r
7624 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
\r
7625 #define EXTI_SWIER_SWIER7_Pos (7U)
\r
7626 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
\r
7627 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
\r
7628 #define EXTI_SWIER_SWIER8_Pos (8U)
\r
7629 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
\r
7630 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
\r
7631 #define EXTI_SWIER_SWIER9_Pos (9U)
\r
7632 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
\r
7633 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
\r
7634 #define EXTI_SWIER_SWIER10_Pos (10U)
\r
7635 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
\r
7636 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
\r
7637 #define EXTI_SWIER_SWIER11_Pos (11U)
\r
7638 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
\r
7639 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
\r
7640 #define EXTI_SWIER_SWIER12_Pos (12U)
\r
7641 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
\r
7642 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
\r
7643 #define EXTI_SWIER_SWIER13_Pos (13U)
\r
7644 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
\r
7645 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
\r
7646 #define EXTI_SWIER_SWIER14_Pos (14U)
\r
7647 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
\r
7648 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
\r
7649 #define EXTI_SWIER_SWIER15_Pos (15U)
\r
7650 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
\r
7651 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
\r
7652 #define EXTI_SWIER_SWIER16_Pos (16U)
\r
7653 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
\r
7654 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
\r
7655 #define EXTI_SWIER_SWIER17_Pos (17U)
\r
7656 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
\r
7657 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
\r
7658 #define EXTI_SWIER_SWIER18_Pos (18U)
\r
7659 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
\r
7660 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
\r
7661 #define EXTI_SWIER_SWIER19_Pos (19U)
\r
7662 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
\r
7663 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
\r
7664 #define EXTI_SWIER_SWIER20_Pos (20U)
\r
7665 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
\r
7666 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
\r
7667 #define EXTI_SWIER_SWIER21_Pos (21U)
\r
7668 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
\r
7669 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
\r
7670 #define EXTI_SWIER_SWIER22_Pos (22U)
\r
7671 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
\r
7672 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
\r
7673 #define EXTI_SWIER_SWIER23_Pos (23U)
\r
7674 #define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
\r
7675 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
\r
7676 #define EXTI_SWIER_SWIER24_Pos (24U)
\r
7677 #define EXTI_SWIER_SWIER24_Msk (0x1UL << EXTI_SWIER_SWIER24_Pos) /*!< 0x01000000 */
\r
7678 #define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk /*!< Software Interrupt on line 24 */
\r
7680 /******************* Bit definition for EXTI_PR register ********************/
\r
7681 #define EXTI_PR_PR0_Pos (0U)
\r
7682 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
\r
7683 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
\r
7684 #define EXTI_PR_PR1_Pos (1U)
\r
7685 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
\r
7686 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
\r
7687 #define EXTI_PR_PR2_Pos (2U)
\r
7688 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
\r
7689 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
\r
7690 #define EXTI_PR_PR3_Pos (3U)
\r
7691 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
\r
7692 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
\r
7693 #define EXTI_PR_PR4_Pos (4U)
\r
7694 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
\r
7695 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
\r
7696 #define EXTI_PR_PR5_Pos (5U)
\r
7697 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
\r
7698 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
\r
7699 #define EXTI_PR_PR6_Pos (6U)
\r
7700 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
\r
7701 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
\r
7702 #define EXTI_PR_PR7_Pos (7U)
\r
7703 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
\r
7704 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
\r
7705 #define EXTI_PR_PR8_Pos (8U)
\r
7706 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
\r
7707 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
\r
7708 #define EXTI_PR_PR9_Pos (9U)
\r
7709 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
\r
7710 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
\r
7711 #define EXTI_PR_PR10_Pos (10U)
\r
7712 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
\r
7713 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
\r
7714 #define EXTI_PR_PR11_Pos (11U)
\r
7715 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
\r
7716 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
\r
7717 #define EXTI_PR_PR12_Pos (12U)
\r
7718 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
\r
7719 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
\r
7720 #define EXTI_PR_PR13_Pos (13U)
\r
7721 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
\r
7722 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
\r
7723 #define EXTI_PR_PR14_Pos (14U)
\r
7724 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
\r
7725 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
\r
7726 #define EXTI_PR_PR15_Pos (15U)
\r
7727 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
\r
7728 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
\r
7729 #define EXTI_PR_PR16_Pos (16U)
\r
7730 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
\r
7731 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
\r
7732 #define EXTI_PR_PR17_Pos (17U)
\r
7733 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
\r
7734 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
\r
7735 #define EXTI_PR_PR18_Pos (18U)
\r
7736 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
\r
7737 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
\r
7738 #define EXTI_PR_PR19_Pos (19U)
\r
7739 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
\r
7740 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
\r
7741 #define EXTI_PR_PR20_Pos (20U)
\r
7742 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
\r
7743 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
\r
7744 #define EXTI_PR_PR21_Pos (21U)
\r
7745 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
\r
7746 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
\r
7747 #define EXTI_PR_PR22_Pos (22U)
\r
7748 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
\r
7749 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
\r
7750 #define EXTI_PR_PR23_Pos (23U)
\r
7751 #define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
\r
7752 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
\r
7753 #define EXTI_PR_PR24_Pos (24U)
\r
7754 #define EXTI_PR_PR24_Msk (0x1UL << EXTI_PR_PR24_Pos) /*!< 0x01000000 */
\r
7755 #define EXTI_PR_PR24 EXTI_PR_PR24_Msk /*!< Pending bit for line 24 */
\r
7757 /******************************************************************************/
\r
7761 /******************************************************************************/
\r
7763 * @brief FLASH Total Sectors Number
\r
7765 #define FLASH_SECTOR_TOTAL 24
\r
7767 /******************* Bits definition for FLASH_ACR register *****************/
\r
7768 #define FLASH_ACR_LATENCY_Pos (0U)
\r
7769 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
\r
7770 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
\r
7771 #define FLASH_ACR_LATENCY_0WS 0x00000000U
\r
7772 #define FLASH_ACR_LATENCY_1WS 0x00000001U
\r
7773 #define FLASH_ACR_LATENCY_2WS 0x00000002U
\r
7774 #define FLASH_ACR_LATENCY_3WS 0x00000003U
\r
7775 #define FLASH_ACR_LATENCY_4WS 0x00000004U
\r
7776 #define FLASH_ACR_LATENCY_5WS 0x00000005U
\r
7777 #define FLASH_ACR_LATENCY_6WS 0x00000006U
\r
7778 #define FLASH_ACR_LATENCY_7WS 0x00000007U
\r
7779 #define FLASH_ACR_LATENCY_8WS 0x00000008U
\r
7780 #define FLASH_ACR_LATENCY_9WS 0x00000009U
\r
7781 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
\r
7782 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
\r
7783 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
\r
7784 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
\r
7785 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
\r
7786 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
\r
7787 #define FLASH_ACR_PRFTEN_Pos (8U)
\r
7788 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
\r
7789 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
\r
7790 #define FLASH_ACR_ARTEN_Pos (9U)
\r
7791 #define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */
\r
7792 #define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
\r
7793 #define FLASH_ACR_ARTRST_Pos (11U)
\r
7794 #define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */
\r
7795 #define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
\r
7797 /******************* Bits definition for FLASH_SR register ******************/
\r
7798 #define FLASH_SR_EOP_Pos (0U)
\r
7799 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
\r
7800 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
\r
7801 #define FLASH_SR_OPERR_Pos (1U)
\r
7802 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
\r
7803 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
\r
7804 #define FLASH_SR_WRPERR_Pos (4U)
\r
7805 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
\r
7806 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
\r
7807 #define FLASH_SR_PGAERR_Pos (5U)
\r
7808 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
\r
7809 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
\r
7810 #define FLASH_SR_PGPERR_Pos (6U)
\r
7811 #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
\r
7812 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
\r
7813 #define FLASH_SR_ERSERR_Pos (7U)
\r
7814 #define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */
\r
7815 #define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
\r
7816 #define FLASH_SR_BSY_Pos (16U)
\r
7817 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
\r
7818 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
\r
7820 /******************* Bits definition for FLASH_CR register ******************/
\r
7821 #define FLASH_CR_PG_Pos (0U)
\r
7822 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
\r
7823 #define FLASH_CR_PG FLASH_CR_PG_Msk
\r
7824 #define FLASH_CR_SER_Pos (1U)
\r
7825 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
\r
7826 #define FLASH_CR_SER FLASH_CR_SER_Msk
\r
7827 #define FLASH_CR_MER_Pos (2U)
\r
7828 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
\r
7829 #define FLASH_CR_MER FLASH_CR_MER_Msk
\r
7830 #define FLASH_CR_MER1 FLASH_CR_MER
\r
7831 #define FLASH_CR_SNB_Pos (3U)
\r
7832 #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
\r
7833 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
\r
7834 #define FLASH_CR_SNB_0 0x00000008U
\r
7835 #define FLASH_CR_SNB_1 0x00000010U
\r
7836 #define FLASH_CR_SNB_2 0x00000020U
\r
7837 #define FLASH_CR_SNB_3 0x00000040U
\r
7838 #define FLASH_CR_SNB_4 0x00000080U
\r
7839 #define FLASH_CR_PSIZE_Pos (8U)
\r
7840 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
\r
7841 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
\r
7842 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
\r
7843 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
\r
7844 #define FLASH_CR_MER2_Pos (15U)
\r
7845 #define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
\r
7846 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
\r
7847 #define FLASH_CR_STRT_Pos (16U)
\r
7848 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
\r
7849 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
\r
7850 #define FLASH_CR_EOPIE_Pos (24U)
\r
7851 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
\r
7852 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
\r
7853 #define FLASH_CR_ERRIE_Pos (25U)
\r
7854 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
\r
7855 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
\r
7856 #define FLASH_CR_LOCK_Pos (31U)
\r
7857 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
\r
7858 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
\r
7860 /******************* Bits definition for FLASH_OPTCR register ***************/
\r
7861 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
\r
7862 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
\r
7863 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
\r
7864 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
\r
7865 #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
\r
7866 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
\r
7867 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
\r
7868 #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
\r
7869 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
\r
7870 #define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */
\r
7871 #define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */
\r
7872 #define FLASH_OPTCR_WWDG_SW_Pos (4U)
\r
7873 #define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */
\r
7874 #define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
\r
7875 #define FLASH_OPTCR_IWDG_SW_Pos (5U)
\r
7876 #define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */
\r
7877 #define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
\r
7878 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
\r
7879 #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
\r
7880 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
\r
7881 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
\r
7882 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
\r
7883 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
\r
7884 #define FLASH_OPTCR_RDP_Pos (8U)
\r
7885 #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
\r
7886 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
\r
7887 #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
\r
7888 #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
\r
7889 #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
\r
7890 #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
\r
7891 #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
\r
7892 #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
\r
7893 #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
\r
7894 #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
\r
7895 #define FLASH_OPTCR_nWRP_Pos (16U)
\r
7896 #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
\r
7897 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
\r
7898 #define FLASH_OPTCR_nWRP_0 0x00010000U
\r
7899 #define FLASH_OPTCR_nWRP_1 0x00020000U
\r
7900 #define FLASH_OPTCR_nWRP_2 0x00040000U
\r
7901 #define FLASH_OPTCR_nWRP_3 0x00080000U
\r
7902 #define FLASH_OPTCR_nWRP_4 0x00100000U
\r
7903 #define FLASH_OPTCR_nWRP_5 0x00200000U
\r
7904 #define FLASH_OPTCR_nWRP_6 0x00400000U
\r
7905 #define FLASH_OPTCR_nWRP_7 0x00800000U
\r
7906 #define FLASH_OPTCR_nWRP_8 0x01000000U
\r
7907 #define FLASH_OPTCR_nWRP_9 0x02000000U
\r
7908 #define FLASH_OPTCR_nWRP_10 0x04000000U
\r
7909 #define FLASH_OPTCR_nWRP_11 0x08000000U
\r
7910 #define FLASH_OPTCR_nDBOOT_Pos (28U)
\r
7911 #define FLASH_OPTCR_nDBOOT_Msk (0x1UL << FLASH_OPTCR_nDBOOT_Pos) /*!< 0x10000000 */
\r
7912 #define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk
\r
7913 #define FLASH_OPTCR_nDBANK_Pos (29U)
\r
7914 #define FLASH_OPTCR_nDBANK_Msk (0x1UL << FLASH_OPTCR_nDBANK_Pos) /*!< 0x20000000 */
\r
7915 #define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk
\r
7916 #define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
\r
7917 #define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */
\r
7918 #define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
\r
7919 #define FLASH_OPTCR_IWDG_STOP_Pos (31U)
\r
7920 #define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */
\r
7921 #define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
\r
7923 /******************* Bits definition for FLASH_OPTCR1 register ***************/
\r
7924 #define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
\r
7925 #define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
\r
7926 #define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
\r
7927 #define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
\r
7928 #define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
\r
7929 #define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
\r
7932 /******************************************************************************/
\r
7934 /* Flexible Memory Controller */
\r
7936 /******************************************************************************/
\r
7937 /****************** Bit definition for FMC_BCR1 register *******************/
\r
7938 #define FMC_BCR1_MBKEN_Pos (0U)
\r
7939 #define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
\r
7940 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
\r
7941 #define FMC_BCR1_MUXEN_Pos (1U)
\r
7942 #define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
\r
7943 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
\r
7944 #define FMC_BCR1_MTYP_Pos (2U)
\r
7945 #define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
\r
7946 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
\r
7947 #define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
\r
7948 #define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
\r
7949 #define FMC_BCR1_MWID_Pos (4U)
\r
7950 #define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
\r
7951 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
\r
7952 #define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
\r
7953 #define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
\r
7954 #define FMC_BCR1_FACCEN_Pos (6U)
\r
7955 #define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
\r
7956 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
\r
7957 #define FMC_BCR1_BURSTEN_Pos (8U)
\r
7958 #define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
\r
7959 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
\r
7960 #define FMC_BCR1_WAITPOL_Pos (9U)
\r
7961 #define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
\r
7962 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
\r
7963 #define FMC_BCR1_WRAPMOD_Pos (10U)
\r
7964 #define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
\r
7965 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
\r
7966 #define FMC_BCR1_WAITCFG_Pos (11U)
\r
7967 #define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
\r
7968 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
\r
7969 #define FMC_BCR1_WREN_Pos (12U)
\r
7970 #define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
\r
7971 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
\r
7972 #define FMC_BCR1_WAITEN_Pos (13U)
\r
7973 #define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
\r
7974 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
\r
7975 #define FMC_BCR1_EXTMOD_Pos (14U)
\r
7976 #define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
\r
7977 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
\r
7978 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
\r
7979 #define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
\r
7980 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
\r
7981 #define FMC_BCR1_CPSIZE_Pos (16U)
\r
7982 #define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
\r
7983 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
\r
7984 #define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
\r
7985 #define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
\r
7986 #define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
\r
7987 #define FMC_BCR1_CBURSTRW_Pos (19U)
\r
7988 #define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
\r
7989 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
\r
7990 #define FMC_BCR1_CCLKEN_Pos (20U)
\r
7991 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
\r
7992 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
\r
7993 #define FMC_BCR1_WFDIS_Pos (21U)
\r
7994 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
\r
7995 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
\r
7997 /****************** Bit definition for FMC_BCR2 register *******************/
\r
7998 #define FMC_BCR2_MBKEN_Pos (0U)
\r
7999 #define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
\r
8000 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
\r
8001 #define FMC_BCR2_MUXEN_Pos (1U)
\r
8002 #define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
\r
8003 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
\r
8004 #define FMC_BCR2_MTYP_Pos (2U)
\r
8005 #define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
\r
8006 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
\r
8007 #define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
\r
8008 #define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
\r
8009 #define FMC_BCR2_MWID_Pos (4U)
\r
8010 #define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
\r
8011 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
\r
8012 #define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
\r
8013 #define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
\r
8014 #define FMC_BCR2_FACCEN_Pos (6U)
\r
8015 #define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
\r
8016 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
\r
8017 #define FMC_BCR2_BURSTEN_Pos (8U)
\r
8018 #define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
\r
8019 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
\r
8020 #define FMC_BCR2_WAITPOL_Pos (9U)
\r
8021 #define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
\r
8022 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
\r
8023 #define FMC_BCR2_WRAPMOD_Pos (10U)
\r
8024 #define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
\r
8025 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
\r
8026 #define FMC_BCR2_WAITCFG_Pos (11U)
\r
8027 #define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
\r
8028 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
\r
8029 #define FMC_BCR2_WREN_Pos (12U)
\r
8030 #define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
\r
8031 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
\r
8032 #define FMC_BCR2_WAITEN_Pos (13U)
\r
8033 #define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
\r
8034 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
\r
8035 #define FMC_BCR2_EXTMOD_Pos (14U)
\r
8036 #define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
\r
8037 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
\r
8038 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
\r
8039 #define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
\r
8040 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
\r
8041 #define FMC_BCR2_CPSIZE_Pos (16U)
\r
8042 #define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
\r
8043 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
\r
8044 #define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
\r
8045 #define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
\r
8046 #define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
\r
8047 #define FMC_BCR2_CBURSTRW_Pos (19U)
\r
8048 #define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
\r
8049 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
\r
8051 /****************** Bit definition for FMC_BCR3 register *******************/
\r
8052 #define FMC_BCR3_MBKEN_Pos (0U)
\r
8053 #define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
\r
8054 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
\r
8055 #define FMC_BCR3_MUXEN_Pos (1U)
\r
8056 #define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
\r
8057 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
\r
8058 #define FMC_BCR3_MTYP_Pos (2U)
\r
8059 #define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
\r
8060 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
\r
8061 #define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
\r
8062 #define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
\r
8063 #define FMC_BCR3_MWID_Pos (4U)
\r
8064 #define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
\r
8065 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
\r
8066 #define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
\r
8067 #define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
\r
8068 #define FMC_BCR3_FACCEN_Pos (6U)
\r
8069 #define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
\r
8070 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
\r
8071 #define FMC_BCR3_BURSTEN_Pos (8U)
\r
8072 #define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
\r
8073 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
\r
8074 #define FMC_BCR3_WAITPOL_Pos (9U)
\r
8075 #define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
\r
8076 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
\r
8077 #define FMC_BCR3_WRAPMOD_Pos (10U)
\r
8078 #define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
\r
8079 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
\r
8080 #define FMC_BCR3_WAITCFG_Pos (11U)
\r
8081 #define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
\r
8082 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
\r
8083 #define FMC_BCR3_WREN_Pos (12U)
\r
8084 #define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
\r
8085 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
\r
8086 #define FMC_BCR3_WAITEN_Pos (13U)
\r
8087 #define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
\r
8088 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
\r
8089 #define FMC_BCR3_EXTMOD_Pos (14U)
\r
8090 #define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
\r
8091 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
\r
8092 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
\r
8093 #define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
\r
8094 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
\r
8095 #define FMC_BCR3_CPSIZE_Pos (16U)
\r
8096 #define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
\r
8097 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
\r
8098 #define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
\r
8099 #define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
\r
8100 #define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
\r
8101 #define FMC_BCR3_CBURSTRW_Pos (19U)
\r
8102 #define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
\r
8103 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
\r
8105 /****************** Bit definition for FMC_BCR4 register *******************/
\r
8106 #define FMC_BCR4_MBKEN_Pos (0U)
\r
8107 #define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
\r
8108 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
\r
8109 #define FMC_BCR4_MUXEN_Pos (1U)
\r
8110 #define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
\r
8111 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
\r
8112 #define FMC_BCR4_MTYP_Pos (2U)
\r
8113 #define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
\r
8114 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
\r
8115 #define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
\r
8116 #define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
\r
8117 #define FMC_BCR4_MWID_Pos (4U)
\r
8118 #define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
\r
8119 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
\r
8120 #define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
\r
8121 #define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
\r
8122 #define FMC_BCR4_FACCEN_Pos (6U)
\r
8123 #define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
\r
8124 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
\r
8125 #define FMC_BCR4_BURSTEN_Pos (8U)
\r
8126 #define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
\r
8127 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
\r
8128 #define FMC_BCR4_WAITPOL_Pos (9U)
\r
8129 #define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
\r
8130 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
\r
8131 #define FMC_BCR4_WRAPMOD_Pos (10U)
\r
8132 #define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
\r
8133 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
\r
8134 #define FMC_BCR4_WAITCFG_Pos (11U)
\r
8135 #define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
\r
8136 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
\r
8137 #define FMC_BCR4_WREN_Pos (12U)
\r
8138 #define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
\r
8139 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
\r
8140 #define FMC_BCR4_WAITEN_Pos (13U)
\r
8141 #define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
\r
8142 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
\r
8143 #define FMC_BCR4_EXTMOD_Pos (14U)
\r
8144 #define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
\r
8145 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
\r
8146 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
\r
8147 #define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
\r
8148 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
\r
8149 #define FMC_BCR4_CPSIZE_Pos (16U)
\r
8150 #define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
\r
8151 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
\r
8152 #define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
\r
8153 #define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
\r
8154 #define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
\r
8155 #define FMC_BCR4_CBURSTRW_Pos (19U)
\r
8156 #define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
\r
8157 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
\r
8159 /****************** Bit definition for FMC_BTR1 register ******************/
\r
8160 #define FMC_BTR1_ADDSET_Pos (0U)
\r
8161 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
\r
8162 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8163 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
\r
8164 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
\r
8165 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
\r
8166 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
\r
8167 #define FMC_BTR1_ADDHLD_Pos (4U)
\r
8168 #define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8169 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8170 #define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
\r
8171 #define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
\r
8172 #define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
\r
8173 #define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
\r
8174 #define FMC_BTR1_DATAST_Pos (8U)
\r
8175 #define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
\r
8176 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8177 #define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
\r
8178 #define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
\r
8179 #define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
\r
8180 #define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
\r
8181 #define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
\r
8182 #define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
\r
8183 #define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
\r
8184 #define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
\r
8185 #define FMC_BTR1_BUSTURN_Pos (16U)
\r
8186 #define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8187 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8188 #define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
\r
8189 #define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
\r
8190 #define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
\r
8191 #define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
\r
8192 #define FMC_BTR1_CLKDIV_Pos (20U)
\r
8193 #define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
\r
8194 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
8195 #define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
\r
8196 #define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
\r
8197 #define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
\r
8198 #define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
\r
8199 #define FMC_BTR1_DATLAT_Pos (24U)
\r
8200 #define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
\r
8201 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
\r
8202 #define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
\r
8203 #define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
\r
8204 #define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
\r
8205 #define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
\r
8206 #define FMC_BTR1_ACCMOD_Pos (28U)
\r
8207 #define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
\r
8208 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8209 #define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
\r
8210 #define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
\r
8212 /****************** Bit definition for FMC_BTR2 register *******************/
\r
8213 #define FMC_BTR2_ADDSET_Pos (0U)
\r
8214 #define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
\r
8215 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8216 #define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
\r
8217 #define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
\r
8218 #define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
\r
8219 #define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
\r
8220 #define FMC_BTR2_ADDHLD_Pos (4U)
\r
8221 #define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8222 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8223 #define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
\r
8224 #define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
\r
8225 #define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
\r
8226 #define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
\r
8227 #define FMC_BTR2_DATAST_Pos (8U)
\r
8228 #define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
\r
8229 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8230 #define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
\r
8231 #define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
\r
8232 #define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
\r
8233 #define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
\r
8234 #define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
\r
8235 #define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
\r
8236 #define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
\r
8237 #define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
\r
8238 #define FMC_BTR2_BUSTURN_Pos (16U)
\r
8239 #define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8240 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8241 #define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
\r
8242 #define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
\r
8243 #define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
\r
8244 #define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
\r
8245 #define FMC_BTR2_CLKDIV_Pos (20U)
\r
8246 #define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
\r
8247 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
8248 #define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
\r
8249 #define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
\r
8250 #define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
\r
8251 #define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
\r
8252 #define FMC_BTR2_DATLAT_Pos (24U)
\r
8253 #define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
\r
8254 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
\r
8255 #define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
\r
8256 #define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
\r
8257 #define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
\r
8258 #define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
\r
8259 #define FMC_BTR2_ACCMOD_Pos (28U)
\r
8260 #define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
\r
8261 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8262 #define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
\r
8263 #define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
\r
8265 /******************* Bit definition for FMC_BTR3 register *******************/
\r
8266 #define FMC_BTR3_ADDSET_Pos (0U)
\r
8267 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
\r
8268 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8269 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
\r
8270 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
\r
8271 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
\r
8272 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
\r
8273 #define FMC_BTR3_ADDHLD_Pos (4U)
\r
8274 #define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8275 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8276 #define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
\r
8277 #define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
\r
8278 #define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
\r
8279 #define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
\r
8280 #define FMC_BTR3_DATAST_Pos (8U)
\r
8281 #define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
\r
8282 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8283 #define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
\r
8284 #define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
\r
8285 #define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
\r
8286 #define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
\r
8287 #define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
\r
8288 #define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
\r
8289 #define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
\r
8290 #define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
\r
8291 #define FMC_BTR3_BUSTURN_Pos (16U)
\r
8292 #define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8293 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8294 #define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
\r
8295 #define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
\r
8296 #define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
\r
8297 #define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
\r
8298 #define FMC_BTR3_CLKDIV_Pos (20U)
\r
8299 #define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
\r
8300 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
8301 #define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
\r
8302 #define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
\r
8303 #define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
\r
8304 #define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
\r
8305 #define FMC_BTR3_DATLAT_Pos (24U)
\r
8306 #define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
\r
8307 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
\r
8308 #define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
\r
8309 #define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
\r
8310 #define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
\r
8311 #define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
\r
8312 #define FMC_BTR3_ACCMOD_Pos (28U)
\r
8313 #define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
\r
8314 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8315 #define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
\r
8316 #define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
\r
8318 /****************** Bit definition for FMC_BTR4 register *******************/
\r
8319 #define FMC_BTR4_ADDSET_Pos (0U)
\r
8320 #define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
\r
8321 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8322 #define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
\r
8323 #define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
\r
8324 #define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
\r
8325 #define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
\r
8326 #define FMC_BTR4_ADDHLD_Pos (4U)
\r
8327 #define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8328 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8329 #define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
\r
8330 #define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
\r
8331 #define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
\r
8332 #define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
\r
8333 #define FMC_BTR4_DATAST_Pos (8U)
\r
8334 #define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
\r
8335 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8336 #define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
\r
8337 #define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
\r
8338 #define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
\r
8339 #define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
\r
8340 #define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
\r
8341 #define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
\r
8342 #define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
\r
8343 #define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
\r
8344 #define FMC_BTR4_BUSTURN_Pos (16U)
\r
8345 #define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8346 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8347 #define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
\r
8348 #define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
\r
8349 #define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
\r
8350 #define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
\r
8351 #define FMC_BTR4_CLKDIV_Pos (20U)
\r
8352 #define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
\r
8353 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
8354 #define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
\r
8355 #define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
\r
8356 #define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
\r
8357 #define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
\r
8358 #define FMC_BTR4_DATLAT_Pos (24U)
\r
8359 #define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
\r
8360 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
\r
8361 #define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
\r
8362 #define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
\r
8363 #define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
\r
8364 #define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
\r
8365 #define FMC_BTR4_ACCMOD_Pos (28U)
\r
8366 #define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
\r
8367 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8368 #define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
\r
8369 #define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
\r
8371 /****************** Bit definition for FMC_BWTR1 register ******************/
\r
8372 #define FMC_BWTR1_ADDSET_Pos (0U)
\r
8373 #define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
\r
8374 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8375 #define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
\r
8376 #define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
\r
8377 #define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
\r
8378 #define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
\r
8379 #define FMC_BWTR1_ADDHLD_Pos (4U)
\r
8380 #define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8381 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8382 #define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
\r
8383 #define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
\r
8384 #define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
\r
8385 #define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
\r
8386 #define FMC_BWTR1_DATAST_Pos (8U)
\r
8387 #define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
\r
8388 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8389 #define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
\r
8390 #define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
\r
8391 #define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
\r
8392 #define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
\r
8393 #define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
\r
8394 #define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
\r
8395 #define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
\r
8396 #define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
\r
8397 #define FMC_BWTR1_BUSTURN_Pos (16U)
\r
8398 #define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8399 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8400 #define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
\r
8401 #define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
\r
8402 #define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
\r
8403 #define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
\r
8404 #define FMC_BWTR1_ACCMOD_Pos (28U)
\r
8405 #define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
\r
8406 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8407 #define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
\r
8408 #define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
\r
8410 /****************** Bit definition for FMC_BWTR2 register ******************/
\r
8411 #define FMC_BWTR2_ADDSET_Pos (0U)
\r
8412 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
\r
8413 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8414 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
\r
8415 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
\r
8416 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
\r
8417 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
\r
8418 #define FMC_BWTR2_ADDHLD_Pos (4U)
\r
8419 #define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8420 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8421 #define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
\r
8422 #define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
\r
8423 #define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
\r
8424 #define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
\r
8425 #define FMC_BWTR2_DATAST_Pos (8U)
\r
8426 #define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
\r
8427 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8428 #define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
\r
8429 #define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
\r
8430 #define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
\r
8431 #define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
\r
8432 #define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
\r
8433 #define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
\r
8434 #define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
\r
8435 #define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
\r
8436 #define FMC_BWTR2_BUSTURN_Pos (16U)
\r
8437 #define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8438 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8439 #define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
\r
8440 #define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
\r
8441 #define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
\r
8442 #define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
\r
8443 #define FMC_BWTR2_ACCMOD_Pos (28U)
\r
8444 #define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
\r
8445 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8446 #define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
\r
8447 #define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
\r
8449 /****************** Bit definition for FMC_BWTR3 register ******************/
\r
8450 #define FMC_BWTR3_ADDSET_Pos (0U)
\r
8451 #define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
\r
8452 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8453 #define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
\r
8454 #define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
\r
8455 #define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
\r
8456 #define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
\r
8457 #define FMC_BWTR3_ADDHLD_Pos (4U)
\r
8458 #define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8459 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8460 #define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
\r
8461 #define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
\r
8462 #define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
\r
8463 #define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
\r
8464 #define FMC_BWTR3_DATAST_Pos (8U)
\r
8465 #define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
\r
8466 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8467 #define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
\r
8468 #define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
\r
8469 #define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
\r
8470 #define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
\r
8471 #define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
\r
8472 #define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
\r
8473 #define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
\r
8474 #define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
\r
8475 #define FMC_BWTR3_BUSTURN_Pos (16U)
\r
8476 #define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8477 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8478 #define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
\r
8479 #define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
\r
8480 #define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
\r
8481 #define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
\r
8482 #define FMC_BWTR3_ACCMOD_Pos (28U)
\r
8483 #define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
\r
8484 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8485 #define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
\r
8486 #define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
\r
8488 /****************** Bit definition for FMC_BWTR4 register ******************/
\r
8489 #define FMC_BWTR4_ADDSET_Pos (0U)
\r
8490 #define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
\r
8491 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
8492 #define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
\r
8493 #define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
\r
8494 #define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
\r
8495 #define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
\r
8496 #define FMC_BWTR4_ADDHLD_Pos (4U)
\r
8497 #define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
\r
8498 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
8499 #define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
\r
8500 #define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
\r
8501 #define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
\r
8502 #define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
\r
8503 #define FMC_BWTR4_DATAST_Pos (8U)
\r
8504 #define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
\r
8505 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
8506 #define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
\r
8507 #define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
\r
8508 #define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
\r
8509 #define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
\r
8510 #define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
\r
8511 #define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
\r
8512 #define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
\r
8513 #define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
\r
8514 #define FMC_BWTR4_BUSTURN_Pos (16U)
\r
8515 #define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
\r
8516 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
8517 #define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
\r
8518 #define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
\r
8519 #define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
\r
8520 #define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
\r
8521 #define FMC_BWTR4_ACCMOD_Pos (28U)
\r
8522 #define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
\r
8523 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
8524 #define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
\r
8525 #define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
\r
8527 /****************** Bit definition for FMC_PCR register *******************/
\r
8528 #define FMC_PCR_PWAITEN_Pos (1U)
\r
8529 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
\r
8530 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
\r
8531 #define FMC_PCR_PBKEN_Pos (2U)
\r
8532 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
\r
8533 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
\r
8534 #define FMC_PCR_PTYP_Pos (3U)
\r
8535 #define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
\r
8536 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
\r
8537 #define FMC_PCR_PWID_Pos (4U)
\r
8538 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
\r
8539 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
\r
8540 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
\r
8541 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
\r
8542 #define FMC_PCR_ECCEN_Pos (6U)
\r
8543 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
\r
8544 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
\r
8545 #define FMC_PCR_TCLR_Pos (9U)
\r
8546 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
\r
8547 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
\r
8548 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
\r
8549 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
\r
8550 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
\r
8551 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
\r
8552 #define FMC_PCR_TAR_Pos (13U)
\r
8553 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
\r
8554 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
\r
8555 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
\r
8556 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
\r
8557 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
\r
8558 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
\r
8559 #define FMC_PCR_ECCPS_Pos (17U)
\r
8560 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
\r
8561 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
\r
8562 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
\r
8563 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
\r
8564 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
\r
8566 /******************* Bit definition for FMC_SR register *******************/
\r
8567 #define FMC_SR_IRS_Pos (0U)
\r
8568 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
\r
8569 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
\r
8570 #define FMC_SR_ILS_Pos (1U)
\r
8571 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
\r
8572 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
\r
8573 #define FMC_SR_IFS_Pos (2U)
\r
8574 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
\r
8575 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
\r
8576 #define FMC_SR_IREN_Pos (3U)
\r
8577 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
\r
8578 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
\r
8579 #define FMC_SR_ILEN_Pos (4U)
\r
8580 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
\r
8581 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
\r
8582 #define FMC_SR_IFEN_Pos (5U)
\r
8583 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
\r
8584 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
\r
8585 #define FMC_SR_FEMPT_Pos (6U)
\r
8586 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
\r
8587 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
\r
8589 /****************** Bit definition for FMC_PMEM register ******************/
\r
8590 #define FMC_PMEM_MEMSET3_Pos (0U)
\r
8591 #define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
\r
8592 #define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
\r
8593 #define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
\r
8594 #define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
\r
8595 #define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
\r
8596 #define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
\r
8597 #define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
\r
8598 #define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
\r
8599 #define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
\r
8600 #define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
\r
8601 #define FMC_PMEM_MEMWAIT3_Pos (8U)
\r
8602 #define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
\r
8603 #define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
\r
8604 #define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
\r
8605 #define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
\r
8606 #define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
\r
8607 #define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
\r
8608 #define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
\r
8609 #define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
\r
8610 #define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
\r
8611 #define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
\r
8612 #define FMC_PMEM_MEMHOLD3_Pos (16U)
\r
8613 #define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
\r
8614 #define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
\r
8615 #define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
\r
8616 #define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
\r
8617 #define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
\r
8618 #define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
\r
8619 #define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
\r
8620 #define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
\r
8621 #define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
\r
8622 #define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
\r
8623 #define FMC_PMEM_MEMHIZ3_Pos (24U)
\r
8624 #define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
\r
8625 #define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
\r
8626 #define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
\r
8627 #define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
\r
8628 #define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
\r
8629 #define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
\r
8630 #define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
\r
8631 #define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
\r
8632 #define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
\r
8633 #define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
\r
8635 /****************** Bit definition for FMC_PATT register ******************/
\r
8636 #define FMC_PATT_ATTSET3_Pos (0U)
\r
8637 #define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
\r
8638 #define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
\r
8639 #define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
\r
8640 #define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
\r
8641 #define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
\r
8642 #define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
\r
8643 #define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
\r
8644 #define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
\r
8645 #define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
\r
8646 #define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
\r
8647 #define FMC_PATT_ATTWAIT3_Pos (8U)
\r
8648 #define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
\r
8649 #define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
\r
8650 #define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
\r
8651 #define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
\r
8652 #define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
\r
8653 #define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
\r
8654 #define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
\r
8655 #define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
\r
8656 #define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
\r
8657 #define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
\r
8658 #define FMC_PATT_ATTHOLD3_Pos (16U)
\r
8659 #define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
\r
8660 #define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
\r
8661 #define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
\r
8662 #define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
\r
8663 #define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
\r
8664 #define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
\r
8665 #define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
\r
8666 #define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
\r
8667 #define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
\r
8668 #define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
\r
8669 #define FMC_PATT_ATTHIZ3_Pos (24U)
\r
8670 #define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
\r
8671 #define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
\r
8672 #define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
\r
8673 #define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
\r
8674 #define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
\r
8675 #define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
\r
8676 #define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
\r
8677 #define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
\r
8678 #define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
\r
8679 #define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
\r
8681 /****************** Bit definition for FMC_ECCR register ******************/
\r
8682 #define FMC_ECCR_ECC3_Pos (0U)
\r
8683 #define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */
\r
8684 #define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */
\r
8686 /****************** Bit definition for FMC_SDCR1 register ******************/
\r
8687 #define FMC_SDCR1_NC_Pos (0U)
\r
8688 #define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
\r
8689 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
\r
8690 #define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
\r
8691 #define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
\r
8692 #define FMC_SDCR1_NR_Pos (2U)
\r
8693 #define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
\r
8694 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
\r
8695 #define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
\r
8696 #define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
\r
8697 #define FMC_SDCR1_MWID_Pos (4U)
\r
8698 #define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
\r
8699 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
\r
8700 #define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
\r
8701 #define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
\r
8702 #define FMC_SDCR1_NB_Pos (6U)
\r
8703 #define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
\r
8704 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
\r
8705 #define FMC_SDCR1_CAS_Pos (7U)
\r
8706 #define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
\r
8707 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
\r
8708 #define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
\r
8709 #define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
\r
8710 #define FMC_SDCR1_WP_Pos (9U)
\r
8711 #define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
\r
8712 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
\r
8713 #define FMC_SDCR1_SDCLK_Pos (10U)
\r
8714 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
\r
8715 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
\r
8716 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
\r
8717 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
\r
8718 #define FMC_SDCR1_RBURST_Pos (12U)
\r
8719 #define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
\r
8720 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
\r
8721 #define FMC_SDCR1_RPIPE_Pos (13U)
\r
8722 #define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
\r
8723 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
\r
8724 #define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
\r
8725 #define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
\r
8727 /****************** Bit definition for FMC_SDCR2 register ******************/
\r
8728 #define FMC_SDCR2_NC_Pos (0U)
\r
8729 #define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
\r
8730 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
\r
8731 #define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
\r
8732 #define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
\r
8733 #define FMC_SDCR2_NR_Pos (2U)
\r
8734 #define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
\r
8735 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
\r
8736 #define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
\r
8737 #define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
\r
8738 #define FMC_SDCR2_MWID_Pos (4U)
\r
8739 #define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
\r
8740 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
\r
8741 #define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
\r
8742 #define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
\r
8743 #define FMC_SDCR2_NB_Pos (6U)
\r
8744 #define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
\r
8745 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
\r
8746 #define FMC_SDCR2_CAS_Pos (7U)
\r
8747 #define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
\r
8748 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
\r
8749 #define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
\r
8750 #define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
\r
8751 #define FMC_SDCR2_WP_Pos (9U)
\r
8752 #define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
\r
8753 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
\r
8754 #define FMC_SDCR2_SDCLK_Pos (10U)
\r
8755 #define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
\r
8756 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
\r
8757 #define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
\r
8758 #define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
\r
8759 #define FMC_SDCR2_RBURST_Pos (12U)
\r
8760 #define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
\r
8761 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
\r
8762 #define FMC_SDCR2_RPIPE_Pos (13U)
\r
8763 #define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
\r
8764 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
\r
8765 #define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
\r
8766 #define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
\r
8768 /****************** Bit definition for FMC_SDTR1 register ******************/
\r
8769 #define FMC_SDTR1_TMRD_Pos (0U)
\r
8770 #define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
\r
8771 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
\r
8772 #define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
\r
8773 #define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
\r
8774 #define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
\r
8775 #define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
\r
8776 #define FMC_SDTR1_TXSR_Pos (4U)
\r
8777 #define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
\r
8778 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
\r
8779 #define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
\r
8780 #define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
\r
8781 #define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
\r
8782 #define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
\r
8783 #define FMC_SDTR1_TRAS_Pos (8U)
\r
8784 #define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
\r
8785 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
\r
8786 #define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
\r
8787 #define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
\r
8788 #define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
\r
8789 #define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
\r
8790 #define FMC_SDTR1_TRC_Pos (12U)
\r
8791 #define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
\r
8792 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
\r
8793 #define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
\r
8794 #define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
\r
8795 #define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
\r
8796 #define FMC_SDTR1_TWR_Pos (16U)
\r
8797 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
\r
8798 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
\r
8799 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
\r
8800 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
\r
8801 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
\r
8802 #define FMC_SDTR1_TRP_Pos (20U)
\r
8803 #define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
\r
8804 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
\r
8805 #define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
\r
8806 #define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
\r
8807 #define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
\r
8808 #define FMC_SDTR1_TRCD_Pos (24U)
\r
8809 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
\r
8810 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
\r
8811 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
\r
8812 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
\r
8813 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
\r
8815 /****************** Bit definition for FMC_SDTR2 register ******************/
\r
8816 #define FMC_SDTR2_TMRD_Pos (0U)
\r
8817 #define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
\r
8818 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
\r
8819 #define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
\r
8820 #define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
\r
8821 #define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
\r
8822 #define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
\r
8823 #define FMC_SDTR2_TXSR_Pos (4U)
\r
8824 #define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
\r
8825 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
\r
8826 #define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
\r
8827 #define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
\r
8828 #define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
\r
8829 #define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
\r
8830 #define FMC_SDTR2_TRAS_Pos (8U)
\r
8831 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
\r
8832 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
\r
8833 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
\r
8834 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
\r
8835 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
\r
8836 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
\r
8837 #define FMC_SDTR2_TRC_Pos (12U)
\r
8838 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
\r
8839 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
\r
8840 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
\r
8841 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
\r
8842 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
\r
8843 #define FMC_SDTR2_TWR_Pos (16U)
\r
8844 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
\r
8845 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
\r
8846 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
\r
8847 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
\r
8848 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
\r
8849 #define FMC_SDTR2_TRP_Pos (20U)
\r
8850 #define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
\r
8851 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
\r
8852 #define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
\r
8853 #define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
\r
8854 #define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
\r
8855 #define FMC_SDTR2_TRCD_Pos (24U)
\r
8856 #define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
\r
8857 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
\r
8858 #define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
\r
8859 #define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
\r
8860 #define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
\r
8862 /****************** Bit definition for FMC_SDCMR register ******************/
\r
8863 #define FMC_SDCMR_MODE_Pos (0U)
\r
8864 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
\r
8865 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
\r
8866 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
\r
8867 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
\r
8868 #define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
\r
8869 #define FMC_SDCMR_CTB2_Pos (3U)
\r
8870 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
\r
8871 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
\r
8872 #define FMC_SDCMR_CTB1_Pos (4U)
\r
8873 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
\r
8874 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
\r
8875 #define FMC_SDCMR_NRFS_Pos (5U)
\r
8876 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
\r
8877 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
\r
8878 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
\r
8879 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
\r
8880 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
\r
8881 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
\r
8882 #define FMC_SDCMR_MRD_Pos (9U)
\r
8883 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
\r
8884 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
\r
8886 /****************** Bit definition for FMC_SDRTR register ******************/
\r
8887 #define FMC_SDRTR_CRE_Pos (0U)
\r
8888 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
\r
8889 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
\r
8890 #define FMC_SDRTR_COUNT_Pos (1U)
\r
8891 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
\r
8892 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
\r
8893 #define FMC_SDRTR_REIE_Pos (14U)
\r
8894 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
\r
8895 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
\r
8897 /****************** Bit definition for FMC_SDSR register ******************/
\r
8898 #define FMC_SDSR_RE_Pos (0U)
\r
8899 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
\r
8900 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
\r
8901 #define FMC_SDSR_MODES1_Pos (1U)
\r
8902 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
\r
8903 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
\r
8904 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
\r
8905 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
\r
8906 #define FMC_SDSR_MODES2_Pos (3U)
\r
8907 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
\r
8908 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
\r
8909 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
\r
8910 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
\r
8911 #define FMC_SDSR_BUSY_Pos (5U)
\r
8912 #define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
\r
8913 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
\r
8915 /******************************************************************************/
\r
8917 /* General Purpose I/O */
\r
8919 /******************************************************************************/
\r
8920 /****************** Bits definition for GPIO_MODER register *****************/
\r
8921 #define GPIO_MODER_MODER0_Pos (0U)
\r
8922 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
\r
8923 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
\r
8924 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
\r
8925 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
\r
8926 #define GPIO_MODER_MODER1_Pos (2U)
\r
8927 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
\r
8928 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
\r
8929 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
\r
8930 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
\r
8931 #define GPIO_MODER_MODER2_Pos (4U)
\r
8932 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
\r
8933 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
\r
8934 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
\r
8935 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
\r
8936 #define GPIO_MODER_MODER3_Pos (6U)
\r
8937 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
\r
8938 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
\r
8939 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
\r
8940 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
\r
8941 #define GPIO_MODER_MODER4_Pos (8U)
\r
8942 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
\r
8943 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
\r
8944 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
\r
8945 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
\r
8946 #define GPIO_MODER_MODER5_Pos (10U)
\r
8947 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
\r
8948 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
\r
8949 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
\r
8950 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
\r
8951 #define GPIO_MODER_MODER6_Pos (12U)
\r
8952 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
\r
8953 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
\r
8954 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
\r
8955 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
\r
8956 #define GPIO_MODER_MODER7_Pos (14U)
\r
8957 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
\r
8958 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
\r
8959 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
\r
8960 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
\r
8961 #define GPIO_MODER_MODER8_Pos (16U)
\r
8962 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
\r
8963 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
\r
8964 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
\r
8965 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
\r
8966 #define GPIO_MODER_MODER9_Pos (18U)
\r
8967 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
\r
8968 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
\r
8969 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
\r
8970 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
\r
8971 #define GPIO_MODER_MODER10_Pos (20U)
\r
8972 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
\r
8973 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
\r
8974 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
\r
8975 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
\r
8976 #define GPIO_MODER_MODER11_Pos (22U)
\r
8977 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
\r
8978 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
\r
8979 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
\r
8980 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
\r
8981 #define GPIO_MODER_MODER12_Pos (24U)
\r
8982 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
\r
8983 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
\r
8984 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
\r
8985 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
\r
8986 #define GPIO_MODER_MODER13_Pos (26U)
\r
8987 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
\r
8988 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
\r
8989 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
\r
8990 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
\r
8991 #define GPIO_MODER_MODER14_Pos (28U)
\r
8992 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
\r
8993 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
\r
8994 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
\r
8995 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
\r
8996 #define GPIO_MODER_MODER15_Pos (30U)
\r
8997 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
\r
8998 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
\r
8999 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
\r
9000 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
\r
9002 /****************** Bits definition for GPIO_OTYPER register ****************/
\r
9003 #define GPIO_OTYPER_OT_0 0x00000001U
\r
9004 #define GPIO_OTYPER_OT_1 0x00000002U
\r
9005 #define GPIO_OTYPER_OT_2 0x00000004U
\r
9006 #define GPIO_OTYPER_OT_3 0x00000008U
\r
9007 #define GPIO_OTYPER_OT_4 0x00000010U
\r
9008 #define GPIO_OTYPER_OT_5 0x00000020U
\r
9009 #define GPIO_OTYPER_OT_6 0x00000040U
\r
9010 #define GPIO_OTYPER_OT_7 0x00000080U
\r
9011 #define GPIO_OTYPER_OT_8 0x00000100U
\r
9012 #define GPIO_OTYPER_OT_9 0x00000200U
\r
9013 #define GPIO_OTYPER_OT_10 0x00000400U
\r
9014 #define GPIO_OTYPER_OT_11 0x00000800U
\r
9015 #define GPIO_OTYPER_OT_12 0x00001000U
\r
9016 #define GPIO_OTYPER_OT_13 0x00002000U
\r
9017 #define GPIO_OTYPER_OT_14 0x00004000U
\r
9018 #define GPIO_OTYPER_OT_15 0x00008000U
\r
9020 /****************** Bits definition for GPIO_OSPEEDR register ***************/
\r
9021 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
\r
9022 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
\r
9023 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
\r
9024 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
\r
9025 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
\r
9026 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
\r
9027 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
\r
9028 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
\r
9029 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
\r
9030 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
\r
9031 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
\r
9032 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
\r
9033 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
\r
9034 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
\r
9035 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
\r
9036 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
\r
9037 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
\r
9038 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
\r
9039 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
\r
9040 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
\r
9041 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
\r
9042 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
\r
9043 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
\r
9044 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
\r
9045 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
\r
9046 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
\r
9047 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
\r
9048 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
\r
9049 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
\r
9050 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
\r
9051 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
\r
9052 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
\r
9053 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
\r
9054 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
\r
9055 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
\r
9056 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
\r
9057 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
\r
9058 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
\r
9059 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
\r
9060 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
\r
9061 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
\r
9062 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
\r
9063 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
\r
9064 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
\r
9065 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
\r
9066 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
\r
9067 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
\r
9068 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
\r
9069 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
\r
9070 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
\r
9071 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
\r
9072 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
\r
9073 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
\r
9074 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
\r
9075 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
\r
9076 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
\r
9077 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
\r
9078 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
\r
9079 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
\r
9080 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
\r
9081 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
\r
9082 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
\r
9083 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
\r
9084 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
\r
9085 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
\r
9086 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
\r
9087 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
\r
9088 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
\r
9089 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
\r
9090 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
\r
9091 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
\r
9092 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
\r
9093 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
\r
9094 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
\r
9095 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
\r
9096 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
\r
9097 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
\r
9098 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
\r
9099 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
\r
9100 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
\r
9102 /****************** Bits definition for GPIO_PUPDR register *****************/
\r
9103 #define GPIO_PUPDR_PUPDR0_Pos (0U)
\r
9104 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
\r
9105 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
\r
9106 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
\r
9107 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
\r
9108 #define GPIO_PUPDR_PUPDR1_Pos (2U)
\r
9109 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
\r
9110 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
\r
9111 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
\r
9112 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
\r
9113 #define GPIO_PUPDR_PUPDR2_Pos (4U)
\r
9114 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
\r
9115 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
\r
9116 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
\r
9117 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
\r
9118 #define GPIO_PUPDR_PUPDR3_Pos (6U)
\r
9119 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
\r
9120 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
\r
9121 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
\r
9122 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
\r
9123 #define GPIO_PUPDR_PUPDR4_Pos (8U)
\r
9124 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
\r
9125 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
\r
9126 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
\r
9127 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
\r
9128 #define GPIO_PUPDR_PUPDR5_Pos (10U)
\r
9129 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
\r
9130 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
\r
9131 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
\r
9132 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
\r
9133 #define GPIO_PUPDR_PUPDR6_Pos (12U)
\r
9134 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
\r
9135 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
\r
9136 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
\r
9137 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
\r
9138 #define GPIO_PUPDR_PUPDR7_Pos (14U)
\r
9139 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
\r
9140 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
\r
9141 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
\r
9142 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
\r
9143 #define GPIO_PUPDR_PUPDR8_Pos (16U)
\r
9144 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
\r
9145 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
\r
9146 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
\r
9147 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
\r
9148 #define GPIO_PUPDR_PUPDR9_Pos (18U)
\r
9149 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
\r
9150 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
\r
9151 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
\r
9152 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
\r
9153 #define GPIO_PUPDR_PUPDR10_Pos (20U)
\r
9154 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
\r
9155 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
\r
9156 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
\r
9157 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
\r
9158 #define GPIO_PUPDR_PUPDR11_Pos (22U)
\r
9159 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
\r
9160 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
\r
9161 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
\r
9162 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
\r
9163 #define GPIO_PUPDR_PUPDR12_Pos (24U)
\r
9164 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
\r
9165 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
\r
9166 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
\r
9167 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
\r
9168 #define GPIO_PUPDR_PUPDR13_Pos (26U)
\r
9169 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
\r
9170 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
\r
9171 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
\r
9172 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
\r
9173 #define GPIO_PUPDR_PUPDR14_Pos (28U)
\r
9174 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
\r
9175 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
\r
9176 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
\r
9177 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
\r
9178 #define GPIO_PUPDR_PUPDR15_Pos (30U)
\r
9179 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
\r
9180 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
\r
9181 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
\r
9182 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
\r
9184 /****************** Bits definition for GPIO_IDR register *******************/
\r
9185 #define GPIO_IDR_IDR_0 0x00000001U
\r
9186 #define GPIO_IDR_IDR_1 0x00000002U
\r
9187 #define GPIO_IDR_IDR_2 0x00000004U
\r
9188 #define GPIO_IDR_IDR_3 0x00000008U
\r
9189 #define GPIO_IDR_IDR_4 0x00000010U
\r
9190 #define GPIO_IDR_IDR_5 0x00000020U
\r
9191 #define GPIO_IDR_IDR_6 0x00000040U
\r
9192 #define GPIO_IDR_IDR_7 0x00000080U
\r
9193 #define GPIO_IDR_IDR_8 0x00000100U
\r
9194 #define GPIO_IDR_IDR_9 0x00000200U
\r
9195 #define GPIO_IDR_IDR_10 0x00000400U
\r
9196 #define GPIO_IDR_IDR_11 0x00000800U
\r
9197 #define GPIO_IDR_IDR_12 0x00001000U
\r
9198 #define GPIO_IDR_IDR_13 0x00002000U
\r
9199 #define GPIO_IDR_IDR_14 0x00004000U
\r
9200 #define GPIO_IDR_IDR_15 0x00008000U
\r
9202 /****************** Bits definition for GPIO_ODR register *******************/
\r
9203 #define GPIO_ODR_ODR_0 0x00000001U
\r
9204 #define GPIO_ODR_ODR_1 0x00000002U
\r
9205 #define GPIO_ODR_ODR_2 0x00000004U
\r
9206 #define GPIO_ODR_ODR_3 0x00000008U
\r
9207 #define GPIO_ODR_ODR_4 0x00000010U
\r
9208 #define GPIO_ODR_ODR_5 0x00000020U
\r
9209 #define GPIO_ODR_ODR_6 0x00000040U
\r
9210 #define GPIO_ODR_ODR_7 0x00000080U
\r
9211 #define GPIO_ODR_ODR_8 0x00000100U
\r
9212 #define GPIO_ODR_ODR_9 0x00000200U
\r
9213 #define GPIO_ODR_ODR_10 0x00000400U
\r
9214 #define GPIO_ODR_ODR_11 0x00000800U
\r
9215 #define GPIO_ODR_ODR_12 0x00001000U
\r
9216 #define GPIO_ODR_ODR_13 0x00002000U
\r
9217 #define GPIO_ODR_ODR_14 0x00004000U
\r
9218 #define GPIO_ODR_ODR_15 0x00008000U
\r
9220 /****************** Bits definition for GPIO_BSRR register ******************/
\r
9221 #define GPIO_BSRR_BS_0 0x00000001U
\r
9222 #define GPIO_BSRR_BS_1 0x00000002U
\r
9223 #define GPIO_BSRR_BS_2 0x00000004U
\r
9224 #define GPIO_BSRR_BS_3 0x00000008U
\r
9225 #define GPIO_BSRR_BS_4 0x00000010U
\r
9226 #define GPIO_BSRR_BS_5 0x00000020U
\r
9227 #define GPIO_BSRR_BS_6 0x00000040U
\r
9228 #define GPIO_BSRR_BS_7 0x00000080U
\r
9229 #define GPIO_BSRR_BS_8 0x00000100U
\r
9230 #define GPIO_BSRR_BS_9 0x00000200U
\r
9231 #define GPIO_BSRR_BS_10 0x00000400U
\r
9232 #define GPIO_BSRR_BS_11 0x00000800U
\r
9233 #define GPIO_BSRR_BS_12 0x00001000U
\r
9234 #define GPIO_BSRR_BS_13 0x00002000U
\r
9235 #define GPIO_BSRR_BS_14 0x00004000U
\r
9236 #define GPIO_BSRR_BS_15 0x00008000U
\r
9237 #define GPIO_BSRR_BR_0 0x00010000U
\r
9238 #define GPIO_BSRR_BR_1 0x00020000U
\r
9239 #define GPIO_BSRR_BR_2 0x00040000U
\r
9240 #define GPIO_BSRR_BR_3 0x00080000U
\r
9241 #define GPIO_BSRR_BR_4 0x00100000U
\r
9242 #define GPIO_BSRR_BR_5 0x00200000U
\r
9243 #define GPIO_BSRR_BR_6 0x00400000U
\r
9244 #define GPIO_BSRR_BR_7 0x00800000U
\r
9245 #define GPIO_BSRR_BR_8 0x01000000U
\r
9246 #define GPIO_BSRR_BR_9 0x02000000U
\r
9247 #define GPIO_BSRR_BR_10 0x04000000U
\r
9248 #define GPIO_BSRR_BR_11 0x08000000U
\r
9249 #define GPIO_BSRR_BR_12 0x10000000U
\r
9250 #define GPIO_BSRR_BR_13 0x20000000U
\r
9251 #define GPIO_BSRR_BR_14 0x40000000U
\r
9252 #define GPIO_BSRR_BR_15 0x80000000U
\r
9254 /****************** Bit definition for GPIO_LCKR register *********************/
\r
9255 #define GPIO_LCKR_LCK0_Pos (0U)
\r
9256 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
\r
9257 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
\r
9258 #define GPIO_LCKR_LCK1_Pos (1U)
\r
9259 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
\r
9260 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
\r
9261 #define GPIO_LCKR_LCK2_Pos (2U)
\r
9262 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
\r
9263 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
\r
9264 #define GPIO_LCKR_LCK3_Pos (3U)
\r
9265 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
\r
9266 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
\r
9267 #define GPIO_LCKR_LCK4_Pos (4U)
\r
9268 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
\r
9269 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
\r
9270 #define GPIO_LCKR_LCK5_Pos (5U)
\r
9271 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
\r
9272 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
\r
9273 #define GPIO_LCKR_LCK6_Pos (6U)
\r
9274 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
\r
9275 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
\r
9276 #define GPIO_LCKR_LCK7_Pos (7U)
\r
9277 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
\r
9278 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
\r
9279 #define GPIO_LCKR_LCK8_Pos (8U)
\r
9280 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
\r
9281 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
\r
9282 #define GPIO_LCKR_LCK9_Pos (9U)
\r
9283 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
\r
9284 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
\r
9285 #define GPIO_LCKR_LCK10_Pos (10U)
\r
9286 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
\r
9287 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
\r
9288 #define GPIO_LCKR_LCK11_Pos (11U)
\r
9289 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
\r
9290 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
\r
9291 #define GPIO_LCKR_LCK12_Pos (12U)
\r
9292 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
\r
9293 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
\r
9294 #define GPIO_LCKR_LCK13_Pos (13U)
\r
9295 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
\r
9296 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
\r
9297 #define GPIO_LCKR_LCK14_Pos (14U)
\r
9298 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
\r
9299 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
\r
9300 #define GPIO_LCKR_LCK15_Pos (15U)
\r
9301 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
\r
9302 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
\r
9303 #define GPIO_LCKR_LCKK_Pos (16U)
\r
9304 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
\r
9305 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
\r
9307 /****************** Bit definition for GPIO_AFRL register *********************/
\r
9308 #define GPIO_AFRL_AFRL0_Pos (0U)
\r
9309 #define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
\r
9310 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
\r
9311 #define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */
\r
9312 #define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */
\r
9313 #define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */
\r
9314 #define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */
\r
9315 #define GPIO_AFRL_AFRL1_Pos (4U)
\r
9316 #define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
\r
9317 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
\r
9318 #define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */
\r
9319 #define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */
\r
9320 #define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */
\r
9321 #define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */
\r
9322 #define GPIO_AFRL_AFRL2_Pos (8U)
\r
9323 #define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
\r
9324 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
\r
9325 #define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */
\r
9326 #define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */
\r
9327 #define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */
\r
9328 #define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */
\r
9329 #define GPIO_AFRL_AFRL3_Pos (12U)
\r
9330 #define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
\r
9331 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
\r
9332 #define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */
\r
9333 #define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */
\r
9334 #define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */
\r
9335 #define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */
\r
9336 #define GPIO_AFRL_AFRL4_Pos (16U)
\r
9337 #define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
\r
9338 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
\r
9339 #define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */
\r
9340 #define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */
\r
9341 #define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */
\r
9342 #define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */
\r
9343 #define GPIO_AFRL_AFRL5_Pos (20U)
\r
9344 #define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
\r
9345 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
\r
9346 #define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */
\r
9347 #define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */
\r
9348 #define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */
\r
9349 #define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */
\r
9350 #define GPIO_AFRL_AFRL6_Pos (24U)
\r
9351 #define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
\r
9352 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
\r
9353 #define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */
\r
9354 #define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */
\r
9355 #define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */
\r
9356 #define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */
\r
9357 #define GPIO_AFRL_AFRL7_Pos (28U)
\r
9358 #define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
\r
9359 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
\r
9360 #define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */
\r
9361 #define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */
\r
9362 #define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */
\r
9363 #define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */
\r
9365 /****************** Bit definition for GPIO_AFRH register *********************/
\r
9366 #define GPIO_AFRH_AFRH0_Pos (0U)
\r
9367 #define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
\r
9368 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
\r
9369 #define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */
\r
9370 #define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */
\r
9371 #define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */
\r
9372 #define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */
\r
9373 #define GPIO_AFRH_AFRH1_Pos (4U)
\r
9374 #define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
\r
9375 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
\r
9376 #define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */
\r
9377 #define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */
\r
9378 #define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */
\r
9379 #define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */
\r
9380 #define GPIO_AFRH_AFRH2_Pos (8U)
\r
9381 #define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
\r
9382 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
\r
9383 #define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */
\r
9384 #define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */
\r
9385 #define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */
\r
9386 #define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */
\r
9387 #define GPIO_AFRH_AFRH3_Pos (12U)
\r
9388 #define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
\r
9389 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
\r
9390 #define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */
\r
9391 #define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */
\r
9392 #define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */
\r
9393 #define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */
\r
9394 #define GPIO_AFRH_AFRH4_Pos (16U)
\r
9395 #define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
\r
9396 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
\r
9397 #define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */
\r
9398 #define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */
\r
9399 #define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */
\r
9400 #define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */
\r
9401 #define GPIO_AFRH_AFRH5_Pos (20U)
\r
9402 #define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
\r
9403 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
\r
9404 #define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */
\r
9405 #define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */
\r
9406 #define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */
\r
9407 #define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */
\r
9408 #define GPIO_AFRH_AFRH6_Pos (24U)
\r
9409 #define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
\r
9410 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
\r
9411 #define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */
\r
9412 #define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */
\r
9413 #define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */
\r
9414 #define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */
\r
9415 #define GPIO_AFRH_AFRH7_Pos (28U)
\r
9416 #define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
\r
9417 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
\r
9418 #define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */
\r
9419 #define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */
\r
9420 #define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */
\r
9421 #define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */
\r
9424 /******************************************************************************/
\r
9426 /* Inter-integrated Circuit Interface (I2C) */
\r
9428 /******************************************************************************/
\r
9429 /******************* Bit definition for I2C_CR1 register *******************/
\r
9430 #define I2C_CR1_PE_Pos (0U)
\r
9431 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
\r
9432 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
\r
9433 #define I2C_CR1_TXIE_Pos (1U)
\r
9434 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
\r
9435 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
\r
9436 #define I2C_CR1_RXIE_Pos (2U)
\r
9437 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
\r
9438 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
\r
9439 #define I2C_CR1_ADDRIE_Pos (3U)
\r
9440 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
\r
9441 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
\r
9442 #define I2C_CR1_NACKIE_Pos (4U)
\r
9443 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
\r
9444 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
\r
9445 #define I2C_CR1_STOPIE_Pos (5U)
\r
9446 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
\r
9447 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
\r
9448 #define I2C_CR1_TCIE_Pos (6U)
\r
9449 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
\r
9450 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
\r
9451 #define I2C_CR1_ERRIE_Pos (7U)
\r
9452 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
\r
9453 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
\r
9454 #define I2C_CR1_DNF_Pos (8U)
\r
9455 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
\r
9456 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
\r
9457 #define I2C_CR1_ANFOFF_Pos (12U)
\r
9458 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
\r
9459 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
\r
9460 #define I2C_CR1_TXDMAEN_Pos (14U)
\r
9461 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
\r
9462 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
\r
9463 #define I2C_CR1_RXDMAEN_Pos (15U)
\r
9464 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
\r
9465 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
\r
9466 #define I2C_CR1_SBC_Pos (16U)
\r
9467 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
\r
9468 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
\r
9469 #define I2C_CR1_NOSTRETCH_Pos (17U)
\r
9470 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
\r
9471 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
\r
9472 #define I2C_CR1_GCEN_Pos (19U)
\r
9473 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
\r
9474 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
\r
9475 #define I2C_CR1_SMBHEN_Pos (20U)
\r
9476 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
\r
9477 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
\r
9478 #define I2C_CR1_SMBDEN_Pos (21U)
\r
9479 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
\r
9480 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
\r
9481 #define I2C_CR1_ALERTEN_Pos (22U)
\r
9482 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
\r
9483 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
\r
9484 #define I2C_CR1_PECEN_Pos (23U)
\r
9485 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
\r
9486 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
\r
9489 /****************** Bit definition for I2C_CR2 register ********************/
\r
9490 #define I2C_CR2_SADD_Pos (0U)
\r
9491 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
\r
9492 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
\r
9493 #define I2C_CR2_RD_WRN_Pos (10U)
\r
9494 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
\r
9495 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
\r
9496 #define I2C_CR2_ADD10_Pos (11U)
\r
9497 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
\r
9498 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
\r
9499 #define I2C_CR2_HEAD10R_Pos (12U)
\r
9500 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
\r
9501 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
\r
9502 #define I2C_CR2_START_Pos (13U)
\r
9503 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
\r
9504 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
\r
9505 #define I2C_CR2_STOP_Pos (14U)
\r
9506 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
\r
9507 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
\r
9508 #define I2C_CR2_NACK_Pos (15U)
\r
9509 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
\r
9510 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
\r
9511 #define I2C_CR2_NBYTES_Pos (16U)
\r
9512 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
\r
9513 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
\r
9514 #define I2C_CR2_RELOAD_Pos (24U)
\r
9515 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
\r
9516 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
\r
9517 #define I2C_CR2_AUTOEND_Pos (25U)
\r
9518 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
\r
9519 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
\r
9520 #define I2C_CR2_PECBYTE_Pos (26U)
\r
9521 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
\r
9522 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
\r
9524 /******************* Bit definition for I2C_OAR1 register ******************/
\r
9525 #define I2C_OAR1_OA1_Pos (0U)
\r
9526 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
\r
9527 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
\r
9528 #define I2C_OAR1_OA1MODE_Pos (10U)
\r
9529 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
\r
9530 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
\r
9531 #define I2C_OAR1_OA1EN_Pos (15U)
\r
9532 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
\r
9533 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
\r
9535 /******************* Bit definition for I2C_OAR2 register ******************/
\r
9536 #define I2C_OAR2_OA2_Pos (1U)
\r
9537 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
\r
9538 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
\r
9539 #define I2C_OAR2_OA2MSK_Pos (8U)
\r
9540 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
\r
9541 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
\r
9542 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
\r
9543 #define I2C_OAR2_OA2MASK01_Pos (8U)
\r
9544 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
\r
9545 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
\r
9546 #define I2C_OAR2_OA2MASK02_Pos (9U)
\r
9547 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
\r
9548 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
\r
9549 #define I2C_OAR2_OA2MASK03_Pos (8U)
\r
9550 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
\r
9551 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
\r
9552 #define I2C_OAR2_OA2MASK04_Pos (10U)
\r
9553 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
\r
9554 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
\r
9555 #define I2C_OAR2_OA2MASK05_Pos (8U)
\r
9556 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
\r
9557 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
\r
9558 #define I2C_OAR2_OA2MASK06_Pos (9U)
\r
9559 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
\r
9560 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
\r
9561 #define I2C_OAR2_OA2MASK07_Pos (8U)
\r
9562 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
\r
9563 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
\r
9564 #define I2C_OAR2_OA2EN_Pos (15U)
\r
9565 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
\r
9566 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
\r
9568 /******************* Bit definition for I2C_TIMINGR register *******************/
\r
9569 #define I2C_TIMINGR_SCLL_Pos (0U)
\r
9570 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
\r
9571 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
\r
9572 #define I2C_TIMINGR_SCLH_Pos (8U)
\r
9573 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
\r
9574 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
\r
9575 #define I2C_TIMINGR_SDADEL_Pos (16U)
\r
9576 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
\r
9577 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
\r
9578 #define I2C_TIMINGR_SCLDEL_Pos (20U)
\r
9579 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
\r
9580 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
\r
9581 #define I2C_TIMINGR_PRESC_Pos (28U)
\r
9582 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
\r
9583 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
\r
9585 /******************* Bit definition for I2C_TIMEOUTR register *******************/
\r
9586 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
\r
9587 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
\r
9588 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
\r
9589 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
\r
9590 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
\r
9591 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
\r
9592 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
\r
9593 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
\r
9594 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
\r
9595 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
\r
9596 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
\r
9597 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
\r
9598 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
\r
9599 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
\r
9600 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
\r
9602 /****************** Bit definition for I2C_ISR register *********************/
\r
9603 #define I2C_ISR_TXE_Pos (0U)
\r
9604 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
\r
9605 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
\r
9606 #define I2C_ISR_TXIS_Pos (1U)
\r
9607 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
\r
9608 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
\r
9609 #define I2C_ISR_RXNE_Pos (2U)
\r
9610 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
\r
9611 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
\r
9612 #define I2C_ISR_ADDR_Pos (3U)
\r
9613 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
\r
9614 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
\r
9615 #define I2C_ISR_NACKF_Pos (4U)
\r
9616 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
\r
9617 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
\r
9618 #define I2C_ISR_STOPF_Pos (5U)
\r
9619 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
\r
9620 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
\r
9621 #define I2C_ISR_TC_Pos (6U)
\r
9622 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
\r
9623 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
\r
9624 #define I2C_ISR_TCR_Pos (7U)
\r
9625 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
\r
9626 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
\r
9627 #define I2C_ISR_BERR_Pos (8U)
\r
9628 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
\r
9629 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
\r
9630 #define I2C_ISR_ARLO_Pos (9U)
\r
9631 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
\r
9632 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
\r
9633 #define I2C_ISR_OVR_Pos (10U)
\r
9634 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
\r
9635 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
\r
9636 #define I2C_ISR_PECERR_Pos (11U)
\r
9637 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
\r
9638 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
\r
9639 #define I2C_ISR_TIMEOUT_Pos (12U)
\r
9640 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
\r
9641 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
\r
9642 #define I2C_ISR_ALERT_Pos (13U)
\r
9643 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
\r
9644 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
\r
9645 #define I2C_ISR_BUSY_Pos (15U)
\r
9646 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
\r
9647 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
\r
9648 #define I2C_ISR_DIR_Pos (16U)
\r
9649 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
\r
9650 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
\r
9651 #define I2C_ISR_ADDCODE_Pos (17U)
\r
9652 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
\r
9653 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
\r
9655 /****************** Bit definition for I2C_ICR register *********************/
\r
9656 #define I2C_ICR_ADDRCF_Pos (3U)
\r
9657 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
\r
9658 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
\r
9659 #define I2C_ICR_NACKCF_Pos (4U)
\r
9660 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
\r
9661 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
\r
9662 #define I2C_ICR_STOPCF_Pos (5U)
\r
9663 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
\r
9664 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
\r
9665 #define I2C_ICR_BERRCF_Pos (8U)
\r
9666 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
\r
9667 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
\r
9668 #define I2C_ICR_ARLOCF_Pos (9U)
\r
9669 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
\r
9670 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
\r
9671 #define I2C_ICR_OVRCF_Pos (10U)
\r
9672 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
\r
9673 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
\r
9674 #define I2C_ICR_PECCF_Pos (11U)
\r
9675 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
\r
9676 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
\r
9677 #define I2C_ICR_TIMOUTCF_Pos (12U)
\r
9678 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
\r
9679 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
\r
9680 #define I2C_ICR_ALERTCF_Pos (13U)
\r
9681 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
\r
9682 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
\r
9684 /****************** Bit definition for I2C_PECR register *********************/
\r
9685 #define I2C_PECR_PEC_Pos (0U)
\r
9686 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
\r
9687 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
\r
9689 /****************** Bit definition for I2C_RXDR register *********************/
\r
9690 #define I2C_RXDR_RXDATA_Pos (0U)
\r
9691 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
\r
9692 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
\r
9694 /****************** Bit definition for I2C_TXDR register *********************/
\r
9695 #define I2C_TXDR_TXDATA_Pos (0U)
\r
9696 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
\r
9697 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
\r
9700 /******************************************************************************/
\r
9702 /* Independent WATCHDOG */
\r
9704 /******************************************************************************/
\r
9705 /******************* Bit definition for IWDG_KR register ********************/
\r
9706 #define IWDG_KR_KEY_Pos (0U)
\r
9707 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
\r
9708 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
\r
9710 /******************* Bit definition for IWDG_PR register ********************/
\r
9711 #define IWDG_PR_PR_Pos (0U)
\r
9712 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
\r
9713 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
\r
9714 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
\r
9715 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
\r
9716 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
\r
9718 /******************* Bit definition for IWDG_RLR register *******************/
\r
9719 #define IWDG_RLR_RL_Pos (0U)
\r
9720 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
\r
9721 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
\r
9723 /******************* Bit definition for IWDG_SR register ********************/
\r
9724 #define IWDG_SR_PVU_Pos (0U)
\r
9725 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
\r
9726 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
\r
9727 #define IWDG_SR_RVU_Pos (1U)
\r
9728 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
\r
9729 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
\r
9730 #define IWDG_SR_WVU_Pos (2U)
\r
9731 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
\r
9732 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
\r
9734 /******************* Bit definition for IWDG_KR register ********************/
\r
9735 #define IWDG_WINR_WIN_Pos (0U)
\r
9736 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
\r
9737 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
\r
9739 /******************************************************************************/
\r
9741 /* LCD-TFT Display Controller (LTDC) */
\r
9743 /******************************************************************************/
\r
9745 /******************** Bit definition for LTDC_SSCR register *****************/
\r
9747 #define LTDC_SSCR_VSH_Pos (0U)
\r
9748 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
\r
9749 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
\r
9750 #define LTDC_SSCR_HSW_Pos (16U)
\r
9751 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
\r
9752 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
\r
9754 /******************** Bit definition for LTDC_BPCR register *****************/
\r
9756 #define LTDC_BPCR_AVBP_Pos (0U)
\r
9757 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
\r
9758 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
\r
9759 #define LTDC_BPCR_AHBP_Pos (16U)
\r
9760 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
\r
9761 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
\r
9763 /******************** Bit definition for LTDC_AWCR register *****************/
\r
9765 #define LTDC_AWCR_AAH_Pos (0U)
\r
9766 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
\r
9767 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
\r
9768 #define LTDC_AWCR_AAW_Pos (16U)
\r
9769 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
\r
9770 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
\r
9772 /******************** Bit definition for LTDC_TWCR register *****************/
\r
9774 #define LTDC_TWCR_TOTALH_Pos (0U)
\r
9775 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
\r
9776 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
\r
9777 #define LTDC_TWCR_TOTALW_Pos (16U)
\r
9778 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
\r
9779 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
\r
9781 /******************** Bit definition for LTDC_GCR register ******************/
\r
9783 #define LTDC_GCR_LTDCEN_Pos (0U)
\r
9784 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
\r
9785 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
\r
9786 #define LTDC_GCR_DBW_Pos (4U)
\r
9787 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
\r
9788 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
\r
9789 #define LTDC_GCR_DGW_Pos (8U)
\r
9790 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
\r
9791 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
\r
9792 #define LTDC_GCR_DRW_Pos (12U)
\r
9793 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
\r
9794 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
\r
9795 #define LTDC_GCR_DEN_Pos (16U)
\r
9796 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
\r
9797 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
\r
9798 #define LTDC_GCR_PCPOL_Pos (28U)
\r
9799 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
\r
9800 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
\r
9801 #define LTDC_GCR_DEPOL_Pos (29U)
\r
9802 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
\r
9803 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
\r
9804 #define LTDC_GCR_VSPOL_Pos (30U)
\r
9805 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
\r
9806 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
\r
9807 #define LTDC_GCR_HSPOL_Pos (31U)
\r
9808 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
\r
9809 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
\r
9812 /******************** Bit definition for LTDC_SRCR register *****************/
\r
9814 #define LTDC_SRCR_IMR_Pos (0U)
\r
9815 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
\r
9816 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
\r
9817 #define LTDC_SRCR_VBR_Pos (1U)
\r
9818 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
\r
9819 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
\r
9821 /******************** Bit definition for LTDC_BCCR register *****************/
\r
9823 #define LTDC_BCCR_BCBLUE_Pos (0U)
\r
9824 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
\r
9825 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
\r
9826 #define LTDC_BCCR_BCGREEN_Pos (8U)
\r
9827 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
\r
9828 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
\r
9829 #define LTDC_BCCR_BCRED_Pos (16U)
\r
9830 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
\r
9831 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
\r
9833 /******************** Bit definition for LTDC_IER register ******************/
\r
9835 #define LTDC_IER_LIE_Pos (0U)
\r
9836 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
\r
9837 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
\r
9838 #define LTDC_IER_FUIE_Pos (1U)
\r
9839 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
\r
9840 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
\r
9841 #define LTDC_IER_TERRIE_Pos (2U)
\r
9842 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
\r
9843 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
\r
9844 #define LTDC_IER_RRIE_Pos (3U)
\r
9845 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
\r
9846 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
\r
9848 /******************** Bit definition for LTDC_ISR register ******************/
\r
9850 #define LTDC_ISR_LIF_Pos (0U)
\r
9851 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
\r
9852 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
\r
9853 #define LTDC_ISR_FUIF_Pos (1U)
\r
9854 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
\r
9855 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
\r
9856 #define LTDC_ISR_TERRIF_Pos (2U)
\r
9857 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
\r
9858 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
\r
9859 #define LTDC_ISR_RRIF_Pos (3U)
\r
9860 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
\r
9861 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
\r
9863 /******************** Bit definition for LTDC_ICR register ******************/
\r
9865 #define LTDC_ICR_CLIF_Pos (0U)
\r
9866 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
\r
9867 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
\r
9868 #define LTDC_ICR_CFUIF_Pos (1U)
\r
9869 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
\r
9870 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
\r
9871 #define LTDC_ICR_CTERRIF_Pos (2U)
\r
9872 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
\r
9873 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
\r
9874 #define LTDC_ICR_CRRIF_Pos (3U)
\r
9875 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
\r
9876 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
\r
9878 /******************** Bit definition for LTDC_LIPCR register ****************/
\r
9880 #define LTDC_LIPCR_LIPOS_Pos (0U)
\r
9881 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
\r
9882 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
\r
9884 /******************** Bit definition for LTDC_CPSR register *****************/
\r
9886 #define LTDC_CPSR_CYPOS_Pos (0U)
\r
9887 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
\r
9888 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
\r
9889 #define LTDC_CPSR_CXPOS_Pos (16U)
\r
9890 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
\r
9891 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
\r
9893 /******************** Bit definition for LTDC_CDSR register *****************/
\r
9895 #define LTDC_CDSR_VDES_Pos (0U)
\r
9896 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
\r
9897 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
\r
9898 #define LTDC_CDSR_HDES_Pos (1U)
\r
9899 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
\r
9900 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
\r
9901 #define LTDC_CDSR_VSYNCS_Pos (2U)
\r
9902 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
\r
9903 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
\r
9904 #define LTDC_CDSR_HSYNCS_Pos (3U)
\r
9905 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
\r
9906 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
\r
9908 /******************** Bit definition for LTDC_LxCR register *****************/
\r
9910 #define LTDC_LxCR_LEN_Pos (0U)
\r
9911 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
\r
9912 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
\r
9913 #define LTDC_LxCR_COLKEN_Pos (1U)
\r
9914 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
\r
9915 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
\r
9916 #define LTDC_LxCR_CLUTEN_Pos (4U)
\r
9917 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
\r
9918 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
\r
9920 /******************** Bit definition for LTDC_LxWHPCR register **************/
\r
9922 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
\r
9923 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
\r
9924 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
\r
9925 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
\r
9926 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
\r
9927 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
\r
9929 /******************** Bit definition for LTDC_LxWVPCR register **************/
\r
9931 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
\r
9932 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
\r
9933 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
\r
9934 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
\r
9935 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
\r
9936 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
\r
9938 /******************** Bit definition for LTDC_LxCKCR register ***************/
\r
9940 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
\r
9941 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
\r
9942 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
\r
9943 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
\r
9944 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
\r
9945 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
\r
9946 #define LTDC_LxCKCR_CKRED_Pos (16U)
\r
9947 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
\r
9948 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
\r
9950 /******************** Bit definition for LTDC_LxPFCR register ***************/
\r
9952 #define LTDC_LxPFCR_PF_Pos (0U)
\r
9953 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
\r
9954 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
\r
9956 /******************** Bit definition for LTDC_LxCACR register ***************/
\r
9958 #define LTDC_LxCACR_CONSTA_Pos (0U)
\r
9959 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
\r
9960 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
\r
9962 /******************** Bit definition for LTDC_LxDCCR register ***************/
\r
9964 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
\r
9965 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
\r
9966 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
\r
9967 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
\r
9968 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
\r
9969 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
\r
9970 #define LTDC_LxDCCR_DCRED_Pos (16U)
\r
9971 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
\r
9972 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
\r
9973 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
\r
9974 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
\r
9975 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
\r
9977 /******************** Bit definition for LTDC_LxBFCR register ***************/
\r
9979 #define LTDC_LxBFCR_BF2_Pos (0U)
\r
9980 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
\r
9981 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
\r
9982 #define LTDC_LxBFCR_BF1_Pos (8U)
\r
9983 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
\r
9984 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
\r
9986 /******************** Bit definition for LTDC_LxCFBAR register **************/
\r
9988 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
\r
9989 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
\r
9990 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
\r
9992 /******************** Bit definition for LTDC_LxCFBLR register **************/
\r
9994 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
\r
9995 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
\r
9996 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
\r
9997 #define LTDC_LxCFBLR_CFBP_Pos (16U)
\r
9998 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
\r
9999 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
\r
10001 /******************** Bit definition for LTDC_LxCFBLNR register *************/
\r
10003 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
\r
10004 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
\r
10005 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
\r
10007 /******************** Bit definition for LTDC_LxCLUTWR register *************/
\r
10009 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
\r
10010 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
\r
10011 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
\r
10012 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
\r
10013 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
\r
10014 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
\r
10015 #define LTDC_LxCLUTWR_RED_Pos (16U)
\r
10016 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
\r
10017 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
\r
10018 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
\r
10019 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
\r
10020 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
\r
10022 /******************************************************************************/
\r
10024 /* Power Control */
\r
10026 /******************************************************************************/
\r
10027 /******************** Bit definition for PWR_CR1 register ********************/
\r
10028 #define PWR_CR1_LPDS_Pos (0U)
\r
10029 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
\r
10030 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */
\r
10031 #define PWR_CR1_PDDS_Pos (1U)
\r
10032 #define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */
\r
10033 #define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */
\r
10034 #define PWR_CR1_CSBF_Pos (3U)
\r
10035 #define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */
\r
10036 #define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */
\r
10037 #define PWR_CR1_PVDE_Pos (4U)
\r
10038 #define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */
\r
10039 #define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */
\r
10040 #define PWR_CR1_PLS_Pos (5U)
\r
10041 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
\r
10042 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
\r
10043 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
\r
10044 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
\r
10045 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
\r
10047 /*!< PVD level configuration */
\r
10048 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
\r
10049 #define PWR_CR1_PLS_LEV1_Pos (5U)
\r
10050 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
\r
10051 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
\r
10052 #define PWR_CR1_PLS_LEV2_Pos (6U)
\r
10053 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
\r
10054 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
\r
10055 #define PWR_CR1_PLS_LEV3_Pos (5U)
\r
10056 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
\r
10057 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
\r
10058 #define PWR_CR1_PLS_LEV4_Pos (7U)
\r
10059 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
\r
10060 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
\r
10061 #define PWR_CR1_PLS_LEV5_Pos (5U)
\r
10062 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
\r
10063 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
\r
10064 #define PWR_CR1_PLS_LEV6_Pos (6U)
\r
10065 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
\r
10066 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
\r
10067 #define PWR_CR1_PLS_LEV7_Pos (5U)
\r
10068 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
\r
10069 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
\r
10070 #define PWR_CR1_DBP_Pos (8U)
\r
10071 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
\r
10072 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
\r
10073 #define PWR_CR1_FPDS_Pos (9U)
\r
10074 #define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */
\r
10075 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */
\r
10076 #define PWR_CR1_LPUDS_Pos (10U)
\r
10077 #define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */
\r
10078 #define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */
\r
10079 #define PWR_CR1_MRUDS_Pos (11U)
\r
10080 #define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */
\r
10081 #define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */
\r
10082 #define PWR_CR1_ADCDC1_Pos (13U)
\r
10083 #define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */
\r
10084 #define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
\r
10085 #define PWR_CR1_VOS_Pos (14U)
\r
10086 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */
\r
10087 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
\r
10088 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00004000 */
\r
10089 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00008000 */
\r
10090 #define PWR_CR1_ODEN_Pos (16U)
\r
10091 #define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */
\r
10092 #define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */
\r
10093 #define PWR_CR1_ODSWEN_Pos (17U)
\r
10094 #define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */
\r
10095 #define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */
\r
10096 #define PWR_CR1_UDEN_Pos (18U)
\r
10097 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
\r
10098 #define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */
\r
10099 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
\r
10100 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
\r
10102 /******************* Bit definition for PWR_CSR1 register ********************/
\r
10103 #define PWR_CSR1_WUIF_Pos (0U)
\r
10104 #define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */
\r
10105 #define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */
\r
10106 #define PWR_CSR1_SBF_Pos (1U)
\r
10107 #define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */
\r
10108 #define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */
\r
10109 #define PWR_CSR1_PVDO_Pos (2U)
\r
10110 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */
\r
10111 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */
\r
10112 #define PWR_CSR1_BRR_Pos (3U)
\r
10113 #define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */
\r
10114 #define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */
\r
10115 #define PWR_CSR1_EIWUP_Pos (8U)
\r
10116 #define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */
\r
10117 #define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */
\r
10118 #define PWR_CSR1_BRE_Pos (9U)
\r
10119 #define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */
\r
10120 #define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */
\r
10121 #define PWR_CSR1_VOSRDY_Pos (14U)
\r
10122 #define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */
\r
10123 #define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
\r
10124 #define PWR_CSR1_ODRDY_Pos (16U)
\r
10125 #define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */
\r
10126 #define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */
\r
10127 #define PWR_CSR1_ODSWRDY_Pos (17U)
\r
10128 #define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */
\r
10129 #define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */
\r
10130 #define PWR_CSR1_UDRDY_Pos (18U)
\r
10131 #define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */
\r
10132 #define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */
\r
10135 /******************** Bit definition for PWR_CR2 register ********************/
\r
10136 #define PWR_CR2_CWUPF1_Pos (0U)
\r
10137 #define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */
\r
10138 #define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */
\r
10139 #define PWR_CR2_CWUPF2_Pos (1U)
\r
10140 #define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */
\r
10141 #define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */
\r
10142 #define PWR_CR2_CWUPF3_Pos (2U)
\r
10143 #define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */
\r
10144 #define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */
\r
10145 #define PWR_CR2_CWUPF4_Pos (3U)
\r
10146 #define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */
\r
10147 #define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */
\r
10148 #define PWR_CR2_CWUPF5_Pos (4U)
\r
10149 #define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */
\r
10150 #define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */
\r
10151 #define PWR_CR2_CWUPF6_Pos (5U)
\r
10152 #define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */
\r
10153 #define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */
\r
10154 #define PWR_CR2_WUPP1_Pos (8U)
\r
10155 #define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */
\r
10156 #define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */
\r
10157 #define PWR_CR2_WUPP2_Pos (9U)
\r
10158 #define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */
\r
10159 #define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */
\r
10160 #define PWR_CR2_WUPP3_Pos (10U)
\r
10161 #define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */
\r
10162 #define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */
\r
10163 #define PWR_CR2_WUPP4_Pos (11U)
\r
10164 #define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */
\r
10165 #define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */
\r
10166 #define PWR_CR2_WUPP5_Pos (12U)
\r
10167 #define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */
\r
10168 #define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */
\r
10169 #define PWR_CR2_WUPP6_Pos (13U)
\r
10170 #define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */
\r
10171 #define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */
\r
10173 /******************* Bit definition for PWR_CSR2 register ********************/
\r
10174 #define PWR_CSR2_WUPF1_Pos (0U)
\r
10175 #define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */
\r
10176 #define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */
\r
10177 #define PWR_CSR2_WUPF2_Pos (1U)
\r
10178 #define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */
\r
10179 #define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */
\r
10180 #define PWR_CSR2_WUPF3_Pos (2U)
\r
10181 #define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */
\r
10182 #define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */
\r
10183 #define PWR_CSR2_WUPF4_Pos (3U)
\r
10184 #define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */
\r
10185 #define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */
\r
10186 #define PWR_CSR2_WUPF5_Pos (4U)
\r
10187 #define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */
\r
10188 #define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */
\r
10189 #define PWR_CSR2_WUPF6_Pos (5U)
\r
10190 #define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */
\r
10191 #define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */
\r
10192 #define PWR_CSR2_EWUP1_Pos (8U)
\r
10193 #define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */
\r
10194 #define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */
\r
10195 #define PWR_CSR2_EWUP2_Pos (9U)
\r
10196 #define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */
\r
10197 #define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */
\r
10198 #define PWR_CSR2_EWUP3_Pos (10U)
\r
10199 #define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */
\r
10200 #define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */
\r
10201 #define PWR_CSR2_EWUP4_Pos (11U)
\r
10202 #define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */
\r
10203 #define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */
\r
10204 #define PWR_CSR2_EWUP5_Pos (12U)
\r
10205 #define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */
\r
10206 #define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */
\r
10207 #define PWR_CSR2_EWUP6_Pos (13U)
\r
10208 #define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */
\r
10209 #define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */
\r
10211 /******************************************************************************/
\r
10215 /******************************************************************************/
\r
10216 /***************** Bit definition for QUADSPI_CR register *******************/
\r
10217 #define QUADSPI_CR_EN_Pos (0U)
\r
10218 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
\r
10219 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
\r
10220 #define QUADSPI_CR_ABORT_Pos (1U)
\r
10221 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
\r
10222 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
\r
10223 #define QUADSPI_CR_DMAEN_Pos (2U)
\r
10224 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
\r
10225 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
\r
10226 #define QUADSPI_CR_TCEN_Pos (3U)
\r
10227 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
\r
10228 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
\r
10229 #define QUADSPI_CR_SSHIFT_Pos (4U)
\r
10230 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
\r
10231 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
\r
10232 #define QUADSPI_CR_DFM_Pos (6U)
\r
10233 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
\r
10234 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
\r
10235 #define QUADSPI_CR_FSEL_Pos (7U)
\r
10236 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
\r
10237 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
\r
10238 #define QUADSPI_CR_FTHRES_Pos (8U)
\r
10239 #define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
\r
10240 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
\r
10241 #define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
\r
10242 #define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
\r
10243 #define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
\r
10244 #define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
\r
10245 #define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
\r
10246 #define QUADSPI_CR_TEIE_Pos (16U)
\r
10247 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
\r
10248 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
\r
10249 #define QUADSPI_CR_TCIE_Pos (17U)
\r
10250 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
\r
10251 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
\r
10252 #define QUADSPI_CR_FTIE_Pos (18U)
\r
10253 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
\r
10254 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
\r
10255 #define QUADSPI_CR_SMIE_Pos (19U)
\r
10256 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
\r
10257 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
\r
10258 #define QUADSPI_CR_TOIE_Pos (20U)
\r
10259 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
\r
10260 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
\r
10261 #define QUADSPI_CR_APMS_Pos (22U)
\r
10262 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
\r
10263 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
\r
10264 #define QUADSPI_CR_PMM_Pos (23U)
\r
10265 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
\r
10266 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
\r
10267 #define QUADSPI_CR_PRESCALER_Pos (24U)
\r
10268 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
\r
10269 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
\r
10270 #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
\r
10271 #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
\r
10272 #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
\r
10273 #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
\r
10274 #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
\r
10275 #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
\r
10276 #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
\r
10277 #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
\r
10279 /***************** Bit definition for QUADSPI_DCR register ******************/
\r
10280 #define QUADSPI_DCR_CKMODE_Pos (0U)
\r
10281 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
\r
10282 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
\r
10283 #define QUADSPI_DCR_CSHT_Pos (8U)
\r
10284 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
\r
10285 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
\r
10286 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
\r
10287 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
\r
10288 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
\r
10289 #define QUADSPI_DCR_FSIZE_Pos (16U)
\r
10290 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
\r
10291 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
\r
10292 #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
\r
10293 #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
\r
10294 #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
\r
10295 #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
\r
10296 #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
\r
10298 /****************** Bit definition for QUADSPI_SR register *******************/
\r
10299 #define QUADSPI_SR_TEF_Pos (0U)
\r
10300 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
\r
10301 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
\r
10302 #define QUADSPI_SR_TCF_Pos (1U)
\r
10303 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
\r
10304 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
\r
10305 #define QUADSPI_SR_FTF_Pos (2U)
\r
10306 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
\r
10307 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
\r
10308 #define QUADSPI_SR_SMF_Pos (3U)
\r
10309 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
\r
10310 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
\r
10311 #define QUADSPI_SR_TOF_Pos (4U)
\r
10312 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
\r
10313 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
\r
10314 #define QUADSPI_SR_BUSY_Pos (5U)
\r
10315 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
\r
10316 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
\r
10317 #define QUADSPI_SR_FLEVEL_Pos (8U)
\r
10318 #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
\r
10319 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
\r
10320 #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
\r
10321 #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
\r
10322 #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
\r
10323 #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
\r
10324 #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
\r
10325 #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
\r
10327 /****************** Bit definition for QUADSPI_FCR register ******************/
\r
10328 #define QUADSPI_FCR_CTEF_Pos (0U)
\r
10329 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
\r
10330 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
\r
10331 #define QUADSPI_FCR_CTCF_Pos (1U)
\r
10332 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
\r
10333 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
\r
10334 #define QUADSPI_FCR_CSMF_Pos (3U)
\r
10335 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
\r
10336 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
\r
10337 #define QUADSPI_FCR_CTOF_Pos (4U)
\r
10338 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
\r
10339 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
\r
10341 /****************** Bit definition for QUADSPI_DLR register ******************/
\r
10342 #define QUADSPI_DLR_DL_Pos (0U)
\r
10343 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
\r
10344 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
\r
10346 /****************** Bit definition for QUADSPI_CCR register ******************/
\r
10347 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
\r
10348 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
\r
10349 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
\r
10350 #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
\r
10351 #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
\r
10352 #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
\r
10353 #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
\r
10354 #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
\r
10355 #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
\r
10356 #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
\r
10357 #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
\r
10358 #define QUADSPI_CCR_IMODE_Pos (8U)
\r
10359 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
\r
10360 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
\r
10361 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
\r
10362 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
\r
10363 #define QUADSPI_CCR_ADMODE_Pos (10U)
\r
10364 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
\r
10365 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
\r
10366 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
\r
10367 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
\r
10368 #define QUADSPI_CCR_ADSIZE_Pos (12U)
\r
10369 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
\r
10370 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
\r
10371 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
\r
10372 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
\r
10373 #define QUADSPI_CCR_ABMODE_Pos (14U)
\r
10374 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
\r
10375 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
\r
10376 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
\r
10377 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
\r
10378 #define QUADSPI_CCR_ABSIZE_Pos (16U)
\r
10379 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
\r
10380 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
\r
10381 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
\r
10382 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
\r
10383 #define QUADSPI_CCR_DCYC_Pos (18U)
\r
10384 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
\r
10385 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
\r
10386 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
\r
10387 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
\r
10388 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
\r
10389 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
\r
10390 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
\r
10391 #define QUADSPI_CCR_DMODE_Pos (24U)
\r
10392 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
\r
10393 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
\r
10394 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
\r
10395 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
\r
10396 #define QUADSPI_CCR_FMODE_Pos (26U)
\r
10397 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
\r
10398 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
\r
10399 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
\r
10400 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
\r
10401 #define QUADSPI_CCR_SIOO_Pos (28U)
\r
10402 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
\r
10403 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
\r
10404 #define QUADSPI_CCR_DHHC_Pos (30U)
\r
10405 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
\r
10406 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
\r
10407 #define QUADSPI_CCR_DDRM_Pos (31U)
\r
10408 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
\r
10409 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
\r
10410 /****************** Bit definition for QUADSPI_AR register *******************/
\r
10411 #define QUADSPI_AR_ADDRESS_Pos (0U)
\r
10412 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
\r
10413 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
\r
10415 /****************** Bit definition for QUADSPI_ABR register ******************/
\r
10416 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
\r
10417 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
\r
10418 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
\r
10420 /****************** Bit definition for QUADSPI_DR register *******************/
\r
10421 #define QUADSPI_DR_DATA_Pos (0U)
\r
10422 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
\r
10423 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
\r
10425 /****************** Bit definition for QUADSPI_PSMKR register ****************/
\r
10426 #define QUADSPI_PSMKR_MASK_Pos (0U)
\r
10427 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
\r
10428 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
\r
10430 /****************** Bit definition for QUADSPI_PSMAR register ****************/
\r
10431 #define QUADSPI_PSMAR_MATCH_Pos (0U)
\r
10432 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
\r
10433 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
\r
10435 /****************** Bit definition for QUADSPI_PIR register *****************/
\r
10436 #define QUADSPI_PIR_INTERVAL_Pos (0U)
\r
10437 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
\r
10438 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
\r
10440 /****************** Bit definition for QUADSPI_LPTR register *****************/
\r
10441 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
\r
10442 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
\r
10443 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
\r
10445 /******************************************************************************/
\r
10447 /* Reset and Clock Control */
\r
10449 /******************************************************************************/
\r
10450 /******************** Bit definition for RCC_CR register ********************/
\r
10451 #define RCC_CR_HSION_Pos (0U)
\r
10452 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
\r
10453 #define RCC_CR_HSION RCC_CR_HSION_Msk
\r
10454 #define RCC_CR_HSIRDY_Pos (1U)
\r
10455 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
\r
10456 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
\r
10457 #define RCC_CR_HSITRIM_Pos (3U)
\r
10458 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
\r
10459 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
\r
10460 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
\r
10461 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
\r
10462 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
\r
10463 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
\r
10464 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
\r
10465 #define RCC_CR_HSICAL_Pos (8U)
\r
10466 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
\r
10467 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
\r
10468 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
\r
10469 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
\r
10470 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
\r
10471 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
\r
10472 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
\r
10473 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
\r
10474 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
\r
10475 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
\r
10476 #define RCC_CR_HSEON_Pos (16U)
\r
10477 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
\r
10478 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
\r
10479 #define RCC_CR_HSERDY_Pos (17U)
\r
10480 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
\r
10481 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
\r
10482 #define RCC_CR_HSEBYP_Pos (18U)
\r
10483 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
\r
10484 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
\r
10485 #define RCC_CR_CSSON_Pos (19U)
\r
10486 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
\r
10487 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
\r
10488 #define RCC_CR_PLLON_Pos (24U)
\r
10489 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
\r
10490 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
\r
10491 #define RCC_CR_PLLRDY_Pos (25U)
\r
10492 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
\r
10493 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
\r
10494 #define RCC_CR_PLLI2SON_Pos (26U)
\r
10495 #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
\r
10496 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
\r
10497 #define RCC_CR_PLLI2SRDY_Pos (27U)
\r
10498 #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
\r
10499 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
\r
10500 #define RCC_CR_PLLSAION_Pos (28U)
\r
10501 #define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
\r
10502 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
\r
10503 #define RCC_CR_PLLSAIRDY_Pos (29U)
\r
10504 #define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
\r
10505 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
\r
10507 /******************** Bit definition for RCC_PLLCFGR register ***************/
\r
10508 #define RCC_PLLCFGR_PLLM_Pos (0U)
\r
10509 #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
\r
10510 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
\r
10511 #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
\r
10512 #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
\r
10513 #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
\r
10514 #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
\r
10515 #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
\r
10516 #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
\r
10517 #define RCC_PLLCFGR_PLLN_Pos (6U)
\r
10518 #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
\r
10519 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
\r
10520 #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
\r
10521 #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
\r
10522 #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
\r
10523 #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
\r
10524 #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
\r
10525 #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
\r
10526 #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
\r
10527 #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
\r
10528 #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
\r
10529 #define RCC_PLLCFGR_PLLP_Pos (16U)
\r
10530 #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
\r
10531 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
\r
10532 #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
\r
10533 #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
\r
10534 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
\r
10535 #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
\r
10536 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
\r
10537 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
\r
10538 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
\r
10539 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
\r
10540 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
\r
10541 #define RCC_PLLCFGR_PLLQ_Pos (24U)
\r
10542 #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
\r
10543 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
\r
10544 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
\r
10545 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
\r
10546 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
\r
10547 #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
\r
10549 #define RCC_PLLCFGR_PLLR_Pos (28U)
\r
10550 #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
\r
10551 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
\r
10552 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
\r
10553 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
\r
10554 #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
\r
10556 /******************** Bit definition for RCC_CFGR register ******************/
\r
10557 /*!< SW configuration */
\r
10558 #define RCC_CFGR_SW_Pos (0U)
\r
10559 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
\r
10560 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
\r
10561 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
\r
10562 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
\r
10563 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
\r
10564 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
\r
10565 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
\r
10567 /*!< SWS configuration */
\r
10568 #define RCC_CFGR_SWS_Pos (2U)
\r
10569 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
\r
10570 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
\r
10571 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
\r
10572 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
\r
10573 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
\r
10574 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
\r
10575 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
\r
10577 /*!< HPRE configuration */
\r
10578 #define RCC_CFGR_HPRE_Pos (4U)
\r
10579 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
\r
10580 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
\r
10581 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
\r
10582 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
\r
10583 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
\r
10584 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
\r
10586 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
\r
10587 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
\r
10588 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
\r
10589 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
\r
10590 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
\r
10591 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
\r
10592 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
\r
10593 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
\r
10594 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
\r
10596 /*!< PPRE1 configuration */
\r
10597 #define RCC_CFGR_PPRE1_Pos (10U)
\r
10598 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
\r
10599 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
\r
10600 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
\r
10601 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
\r
10602 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
\r
10604 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
\r
10605 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
\r
10606 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
\r
10607 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
\r
10608 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
\r
10610 /*!< PPRE2 configuration */
\r
10611 #define RCC_CFGR_PPRE2_Pos (13U)
\r
10612 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
\r
10613 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
\r
10614 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
\r
10615 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
\r
10616 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
\r
10618 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
\r
10619 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
\r
10620 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
\r
10621 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
\r
10622 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
\r
10624 /*!< RTCPRE configuration */
\r
10625 #define RCC_CFGR_RTCPRE_Pos (16U)
\r
10626 #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
\r
10627 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
\r
10628 #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
\r
10629 #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
\r
10630 #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
\r
10631 #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
\r
10632 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
\r
10634 /*!< MCO1 configuration */
\r
10635 #define RCC_CFGR_MCO1_Pos (21U)
\r
10636 #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
\r
10637 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
\r
10638 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
\r
10639 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
\r
10641 #define RCC_CFGR_I2SSRC_Pos (23U)
\r
10642 #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
\r
10643 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
\r
10645 #define RCC_CFGR_MCO1PRE_Pos (24U)
\r
10646 #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
\r
10647 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
\r
10648 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
\r
10649 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
\r
10650 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
\r
10652 #define RCC_CFGR_MCO2PRE_Pos (27U)
\r
10653 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
\r
10654 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
\r
10655 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
\r
10656 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
\r
10657 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
\r
10659 #define RCC_CFGR_MCO2_Pos (30U)
\r
10660 #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
\r
10661 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
\r
10662 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
\r
10663 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
\r
10665 /******************** Bit definition for RCC_CIR register *******************/
\r
10666 #define RCC_CIR_LSIRDYF_Pos (0U)
\r
10667 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
\r
10668 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
\r
10669 #define RCC_CIR_LSERDYF_Pos (1U)
\r
10670 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
\r
10671 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
\r
10672 #define RCC_CIR_HSIRDYF_Pos (2U)
\r
10673 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
\r
10674 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
\r
10675 #define RCC_CIR_HSERDYF_Pos (3U)
\r
10676 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
\r
10677 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
\r
10678 #define RCC_CIR_PLLRDYF_Pos (4U)
\r
10679 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
\r
10680 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
\r
10681 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
\r
10682 #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
\r
10683 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
\r
10684 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
\r
10685 #define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
\r
10686 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
\r
10687 #define RCC_CIR_CSSF_Pos (7U)
\r
10688 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
\r
10689 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
\r
10690 #define RCC_CIR_LSIRDYIE_Pos (8U)
\r
10691 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
\r
10692 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
\r
10693 #define RCC_CIR_LSERDYIE_Pos (9U)
\r
10694 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
\r
10695 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
\r
10696 #define RCC_CIR_HSIRDYIE_Pos (10U)
\r
10697 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
\r
10698 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
\r
10699 #define RCC_CIR_HSERDYIE_Pos (11U)
\r
10700 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
\r
10701 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
\r
10702 #define RCC_CIR_PLLRDYIE_Pos (12U)
\r
10703 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
\r
10704 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
\r
10705 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
\r
10706 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
\r
10707 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
\r
10708 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
\r
10709 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
\r
10710 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
\r
10711 #define RCC_CIR_LSIRDYC_Pos (16U)
\r
10712 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
\r
10713 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
\r
10714 #define RCC_CIR_LSERDYC_Pos (17U)
\r
10715 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
\r
10716 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
\r
10717 #define RCC_CIR_HSIRDYC_Pos (18U)
\r
10718 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
\r
10719 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
\r
10720 #define RCC_CIR_HSERDYC_Pos (19U)
\r
10721 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
\r
10722 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
\r
10723 #define RCC_CIR_PLLRDYC_Pos (20U)
\r
10724 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
\r
10725 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
\r
10726 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
\r
10727 #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
\r
10728 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
\r
10729 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
\r
10730 #define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
\r
10731 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
\r
10732 #define RCC_CIR_CSSC_Pos (23U)
\r
10733 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
\r
10734 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
\r
10736 /******************** Bit definition for RCC_AHB1RSTR register **************/
\r
10737 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
\r
10738 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
\r
10739 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
\r
10740 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
\r
10741 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
\r
10742 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
\r
10743 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
\r
10744 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
\r
10745 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
\r
10746 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
\r
10747 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
\r
10748 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
\r
10749 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
\r
10750 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
\r
10751 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
\r
10752 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
\r
10753 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
\r
10754 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
\r
10755 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
\r
10756 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
\r
10757 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
\r
10758 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
\r
10759 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
\r
10760 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
\r
10761 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
\r
10762 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
\r
10763 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
\r
10764 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
\r
10765 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
\r
10766 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
\r
10767 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
\r
10768 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
\r
10769 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
\r
10770 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
\r
10771 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
\r
10772 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
\r
10773 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
\r
10774 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
\r
10775 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
\r
10776 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
\r
10777 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
\r
10778 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
\r
10779 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
\r
10780 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
\r
10781 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
\r
10782 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
\r
10783 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
\r
10784 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
\r
10785 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
\r
10786 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
\r
10787 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
\r
10789 /******************** Bit definition for RCC_AHB2RSTR register **************/
\r
10790 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
\r
10791 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
\r
10792 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
\r
10793 #define RCC_AHB2RSTR_JPEGRST_Pos (1U)
\r
10794 #define RCC_AHB2RSTR_JPEGRST_Msk (0x1UL << RCC_AHB2RSTR_JPEGRST_Pos) /*!< 0x00000002 */
\r
10795 #define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk
\r
10796 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
\r
10797 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
\r
10798 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
\r
10799 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
\r
10800 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
\r
10801 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
\r
10803 /******************** Bit definition for RCC_AHB3RSTR register **************/
\r
10805 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
\r
10806 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
\r
10807 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
\r
10808 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
\r
10809 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
\r
10810 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
\r
10812 /******************** Bit definition for RCC_APB1RSTR register **************/
\r
10813 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
\r
10814 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
\r
10815 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
\r
10816 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
\r
10817 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
\r
10818 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
\r
10819 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
\r
10820 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
\r
10821 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
\r
10822 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
\r
10823 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
\r
10824 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
\r
10825 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
\r
10826 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
\r
10827 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
\r
10828 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
\r
10829 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
\r
10830 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
\r
10831 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
\r
10832 #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
\r
10833 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
\r
10834 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
\r
10835 #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
\r
10836 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
\r
10837 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
\r
10838 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
\r
10839 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
\r
10840 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
\r
10841 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
\r
10842 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
\r
10843 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
\r
10844 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
\r
10845 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
\r
10846 #define RCC_APB1RSTR_CAN3RST_Pos (13U)
\r
10847 #define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x00002000 */
\r
10848 #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
\r
10849 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
\r
10850 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
\r
10851 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
\r
10852 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
\r
10853 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
\r
10854 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
\r
10855 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
\r
10856 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
\r
10857 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
\r
10858 #define RCC_APB1RSTR_USART2RST_Pos (17U)
\r
10859 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
\r
10860 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
\r
10861 #define RCC_APB1RSTR_USART3RST_Pos (18U)
\r
10862 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
\r
10863 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
\r
10864 #define RCC_APB1RSTR_UART4RST_Pos (19U)
\r
10865 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
\r
10866 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
\r
10867 #define RCC_APB1RSTR_UART5RST_Pos (20U)
\r
10868 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
\r
10869 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
\r
10870 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
\r
10871 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
\r
10872 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
\r
10873 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
\r
10874 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
\r
10875 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
\r
10876 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
\r
10877 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
\r
10878 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
\r
10879 #define RCC_APB1RSTR_I2C4RST_Pos (24U)
\r
10880 #define RCC_APB1RSTR_I2C4RST_Msk (0x1UL << RCC_APB1RSTR_I2C4RST_Pos) /*!< 0x01000000 */
\r
10881 #define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
\r
10882 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
\r
10883 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
\r
10884 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
\r
10885 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
\r
10886 #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
\r
10887 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
\r
10888 #define RCC_APB1RSTR_CECRST_Pos (27U)
\r
10889 #define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
\r
10890 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
\r
10891 #define RCC_APB1RSTR_PWRRST_Pos (28U)
\r
10892 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
\r
10893 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
\r
10894 #define RCC_APB1RSTR_DACRST_Pos (29U)
\r
10895 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
\r
10896 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
\r
10897 #define RCC_APB1RSTR_UART7RST_Pos (30U)
\r
10898 #define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
\r
10899 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
\r
10900 #define RCC_APB1RSTR_UART8RST_Pos (31U)
\r
10901 #define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
\r
10902 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
\r
10904 /******************** Bit definition for RCC_APB2RSTR register **************/
\r
10905 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
\r
10906 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
\r
10907 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
\r
10908 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
\r
10909 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
\r
10910 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
\r
10911 #define RCC_APB2RSTR_USART1RST_Pos (4U)
\r
10912 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
\r
10913 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
\r
10914 #define RCC_APB2RSTR_USART6RST_Pos (5U)
\r
10915 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
\r
10916 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
\r
10917 #define RCC_APB2RSTR_SDMMC2RST_Pos (7U)
\r
10918 #define RCC_APB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
\r
10919 #define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk
\r
10920 #define RCC_APB2RSTR_ADCRST_Pos (8U)
\r
10921 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
\r
10922 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
\r
10923 #define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
\r
10924 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */
\r
10925 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
\r
10926 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
\r
10927 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
\r
10928 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
\r
10929 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
\r
10930 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
\r
10931 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
\r
10932 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
\r
10933 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
\r
10934 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
\r
10935 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
\r
10936 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
\r
10937 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
\r
10938 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
\r
10939 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
\r
10940 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
\r
10941 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
\r
10942 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
\r
10943 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
\r
10944 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
\r
10945 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
\r
10946 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
\r
10947 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
\r
10948 #define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
\r
10949 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
\r
10950 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
\r
10951 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
\r
10952 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
\r
10953 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
\r
10954 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
\r
10955 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
\r
10956 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
\r
10957 #define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
\r
10958 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
\r
10959 #define RCC_APB2RSTR_DFSDM1RST_Pos (29U)
\r
10960 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x20000000 */
\r
10961 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
\r
10962 #define RCC_APB2RSTR_MDIORST_Pos (30U)
\r
10963 #define RCC_APB2RSTR_MDIORST_Msk (0x1UL << RCC_APB2RSTR_MDIORST_Pos) /*!< 0x40000000 */
\r
10964 #define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk
\r
10966 /******************** Bit definition for RCC_AHB1ENR register ***************/
\r
10967 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
\r
10968 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
\r
10969 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
\r
10970 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
\r
10971 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
\r
10972 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
\r
10973 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
\r
10974 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
\r
10975 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
\r
10976 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
\r
10977 #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
\r
10978 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
\r
10979 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
\r
10980 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
\r
10981 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
\r
10982 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
\r
10983 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
\r
10984 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
\r
10985 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
\r
10986 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
\r
10987 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
\r
10988 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
\r
10989 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
\r
10990 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
\r
10991 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
\r
10992 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
\r
10993 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
\r
10994 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
\r
10995 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
\r
10996 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
\r
10997 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
\r
10998 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
\r
10999 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
\r
11000 #define RCC_AHB1ENR_CRCEN_Pos (12U)
\r
11001 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
\r
11002 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
\r
11003 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
\r
11004 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
\r
11005 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
\r
11006 #define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
\r
11007 #define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */
\r
11008 #define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
\r
11009 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
\r
11010 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
\r
11011 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
\r
11012 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
\r
11013 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
\r
11014 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
\r
11015 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
\r
11016 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
\r
11017 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
\r
11018 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
\r
11019 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
\r
11020 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
\r
11021 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
\r
11022 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
\r
11023 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
\r
11024 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
\r
11025 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
\r
11026 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
\r
11027 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
\r
11028 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
\r
11029 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
\r
11030 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
\r
11031 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
\r
11032 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
\r
11033 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
\r
11034 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
\r
11035 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
\r
11037 /******************** Bit definition for RCC_AHB2ENR register ***************/
\r
11038 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
\r
11039 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
\r
11040 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
\r
11041 #define RCC_AHB2ENR_JPEGEN_Pos (1U)
\r
11042 #define RCC_AHB2ENR_JPEGEN_Msk (0x1UL << RCC_AHB2ENR_JPEGEN_Pos) /*!< 0x00000002 */
\r
11043 #define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk
\r
11044 #define RCC_AHB2ENR_RNGEN_Pos (6U)
\r
11045 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
\r
11046 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
\r
11047 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
\r
11048 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
\r
11049 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
\r
11051 /******************** Bit definition for RCC_AHB3ENR register ***************/
\r
11052 #define RCC_AHB3ENR_FMCEN_Pos (0U)
\r
11053 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
\r
11054 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
\r
11055 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
\r
11056 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
\r
11057 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
\r
11059 /******************** Bit definition for RCC_APB1ENR register ***************/
\r
11060 #define RCC_APB1ENR_TIM2EN_Pos (0U)
\r
11061 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
\r
11062 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
\r
11063 #define RCC_APB1ENR_TIM3EN_Pos (1U)
\r
11064 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
\r
11065 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
\r
11066 #define RCC_APB1ENR_TIM4EN_Pos (2U)
\r
11067 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
\r
11068 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
\r
11069 #define RCC_APB1ENR_TIM5EN_Pos (3U)
\r
11070 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
\r
11071 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
\r
11072 #define RCC_APB1ENR_TIM6EN_Pos (4U)
\r
11073 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
\r
11074 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
\r
11075 #define RCC_APB1ENR_TIM7EN_Pos (5U)
\r
11076 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
\r
11077 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
\r
11078 #define RCC_APB1ENR_TIM12EN_Pos (6U)
\r
11079 #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
\r
11080 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
\r
11081 #define RCC_APB1ENR_TIM13EN_Pos (7U)
\r
11082 #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
\r
11083 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
\r
11084 #define RCC_APB1ENR_TIM14EN_Pos (8U)
\r
11085 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
\r
11086 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
\r
11087 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
\r
11088 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
\r
11089 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
\r
11090 #define RCC_APB1ENR_RTCEN_Pos (10U)
\r
11091 #define RCC_APB1ENR_RTCEN_Msk (0x1UL << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */
\r
11092 #define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
\r
11093 #define RCC_APB1ENR_WWDGEN_Pos (11U)
\r
11094 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
\r
11095 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
\r
11096 #define RCC_APB1ENR_CAN3EN_Pos (13U)
\r
11097 #define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x00002000 */
\r
11098 #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
\r
11099 #define RCC_APB1ENR_SPI2EN_Pos (14U)
\r
11100 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
\r
11101 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
\r
11102 #define RCC_APB1ENR_SPI3EN_Pos (15U)
\r
11103 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
\r
11104 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
\r
11105 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
\r
11106 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
\r
11107 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
\r
11108 #define RCC_APB1ENR_USART2EN_Pos (17U)
\r
11109 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
\r
11110 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
\r
11111 #define RCC_APB1ENR_USART3EN_Pos (18U)
\r
11112 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
\r
11113 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
\r
11114 #define RCC_APB1ENR_UART4EN_Pos (19U)
\r
11115 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
\r
11116 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
\r
11117 #define RCC_APB1ENR_UART5EN_Pos (20U)
\r
11118 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
\r
11119 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
\r
11120 #define RCC_APB1ENR_I2C1EN_Pos (21U)
\r
11121 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
\r
11122 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
\r
11123 #define RCC_APB1ENR_I2C2EN_Pos (22U)
\r
11124 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
\r
11125 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
\r
11126 #define RCC_APB1ENR_I2C3EN_Pos (23U)
\r
11127 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
\r
11128 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
\r
11129 #define RCC_APB1ENR_I2C4EN_Pos (24U)
\r
11130 #define RCC_APB1ENR_I2C4EN_Msk (0x1UL << RCC_APB1ENR_I2C4EN_Pos) /*!< 0x01000000 */
\r
11131 #define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
\r
11132 #define RCC_APB1ENR_CAN1EN_Pos (25U)
\r
11133 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
\r
11134 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
\r
11135 #define RCC_APB1ENR_CAN2EN_Pos (26U)
\r
11136 #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
\r
11137 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
\r
11138 #define RCC_APB1ENR_CECEN_Pos (27U)
\r
11139 #define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
\r
11140 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
\r
11141 #define RCC_APB1ENR_PWREN_Pos (28U)
\r
11142 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
\r
11143 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
\r
11144 #define RCC_APB1ENR_DACEN_Pos (29U)
\r
11145 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
\r
11146 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
\r
11147 #define RCC_APB1ENR_UART7EN_Pos (30U)
\r
11148 #define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
\r
11149 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
\r
11150 #define RCC_APB1ENR_UART8EN_Pos (31U)
\r
11151 #define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
\r
11152 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
\r
11154 /******************** Bit definition for RCC_APB2ENR register ***************/
\r
11155 #define RCC_APB2ENR_TIM1EN_Pos (0U)
\r
11156 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
\r
11157 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
\r
11158 #define RCC_APB2ENR_TIM8EN_Pos (1U)
\r
11159 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
\r
11160 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
\r
11161 #define RCC_APB2ENR_USART1EN_Pos (4U)
\r
11162 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
\r
11163 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
\r
11164 #define RCC_APB2ENR_USART6EN_Pos (5U)
\r
11165 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
\r
11166 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
\r
11167 #define RCC_APB2ENR_SDMMC2EN_Pos (7U)
\r
11168 #define RCC_APB2ENR_SDMMC2EN_Msk (0x1UL << RCC_APB2ENR_SDMMC2EN_Pos) /*!< 0x00000080 */
\r
11169 #define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk
\r
11170 #define RCC_APB2ENR_ADC1EN_Pos (8U)
\r
11171 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
\r
11172 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
\r
11173 #define RCC_APB2ENR_ADC2EN_Pos (9U)
\r
11174 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
\r
11175 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
\r
11176 #define RCC_APB2ENR_ADC3EN_Pos (10U)
\r
11177 #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
\r
11178 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
\r
11179 #define RCC_APB2ENR_SDMMC1EN_Pos (11U)
\r
11180 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */
\r
11181 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
\r
11182 #define RCC_APB2ENR_SPI1EN_Pos (12U)
\r
11183 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
\r
11184 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
\r
11185 #define RCC_APB2ENR_SPI4EN_Pos (13U)
\r
11186 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
\r
11187 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
\r
11188 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
\r
11189 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
\r
11190 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
\r
11191 #define RCC_APB2ENR_TIM9EN_Pos (16U)
\r
11192 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
\r
11193 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
\r
11194 #define RCC_APB2ENR_TIM10EN_Pos (17U)
\r
11195 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
\r
11196 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
\r
11197 #define RCC_APB2ENR_TIM11EN_Pos (18U)
\r
11198 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
\r
11199 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
\r
11200 #define RCC_APB2ENR_SPI5EN_Pos (20U)
\r
11201 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
\r
11202 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
\r
11203 #define RCC_APB2ENR_SPI6EN_Pos (21U)
\r
11204 #define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
\r
11205 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
\r
11206 #define RCC_APB2ENR_SAI1EN_Pos (22U)
\r
11207 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
\r
11208 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
\r
11209 #define RCC_APB2ENR_SAI2EN_Pos (23U)
\r
11210 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
\r
11211 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
\r
11212 #define RCC_APB2ENR_LTDCEN_Pos (26U)
\r
11213 #define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
\r
11214 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
\r
11215 #define RCC_APB2ENR_DFSDM1EN_Pos (29U)
\r
11216 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x20000000 */
\r
11217 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
\r
11218 #define RCC_APB2ENR_MDIOEN_Pos (30U)
\r
11219 #define RCC_APB2ENR_MDIOEN_Msk (0x1UL << RCC_APB2ENR_MDIOEN_Pos) /*!< 0x40000000 */
\r
11220 #define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk
\r
11222 /******************** Bit definition for RCC_AHB1LPENR register *************/
\r
11223 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
\r
11224 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
\r
11225 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
\r
11226 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
\r
11227 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
\r
11228 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
\r
11229 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
\r
11230 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
\r
11231 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
\r
11232 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
\r
11233 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
\r
11234 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
\r
11235 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
\r
11236 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
\r
11237 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
\r
11238 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
\r
11239 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
\r
11240 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
\r
11241 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
\r
11242 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
\r
11243 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
\r
11244 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
\r
11245 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
\r
11246 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
\r
11247 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
\r
11248 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
\r
11249 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
\r
11250 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
\r
11251 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
\r
11252 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
\r
11253 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
\r
11254 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
\r
11255 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
\r
11256 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
\r
11257 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
\r
11258 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
\r
11259 #define RCC_AHB1LPENR_AXILPEN_Pos (13U)
\r
11260 #define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */
\r
11261 #define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
\r
11262 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
\r
11263 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
\r
11264 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
\r
11265 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
\r
11266 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
\r
11267 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
\r
11268 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
\r
11269 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
\r
11270 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
\r
11271 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
\r
11272 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
\r
11273 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
\r
11274 #define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
\r
11275 #define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */
\r
11276 #define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
\r
11277 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
\r
11278 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
\r
11279 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
\r
11280 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
\r
11281 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
\r
11282 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
\r
11283 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
\r
11284 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
\r
11285 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
\r
11286 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
\r
11287 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
\r
11288 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
\r
11289 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
\r
11290 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
\r
11291 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
\r
11292 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
\r
11293 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
\r
11294 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
\r
11295 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
\r
11296 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
\r
11297 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
\r
11298 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
\r
11299 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
\r
11300 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
\r
11301 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
\r
11302 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
\r
11303 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
\r
11305 /******************** Bit definition for RCC_AHB2LPENR register *************/
\r
11306 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
\r
11307 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
\r
11308 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
\r
11309 #define RCC_AHB2LPENR_JPEGLPEN_Pos (1U)
\r
11310 #define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB2LPENR_JPEGLPEN_Pos) /*!< 0x00000002 */
\r
11311 #define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk
\r
11312 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
\r
11313 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
\r
11314 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
\r
11315 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
\r
11316 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
\r
11317 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
\r
11319 /******************** Bit definition for RCC_AHB3LPENR register *************/
\r
11320 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
\r
11321 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
\r
11322 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
\r
11323 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
\r
11324 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
\r
11325 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
\r
11326 /******************** Bit definition for RCC_APB1LPENR register *************/
\r
11327 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
\r
11328 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
\r
11329 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
\r
11330 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
\r
11331 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
\r
11332 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
\r
11333 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
\r
11334 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
\r
11335 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
\r
11336 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
\r
11337 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
\r
11338 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
\r
11339 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
\r
11340 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
\r
11341 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
\r
11342 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
\r
11343 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
\r
11344 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
\r
11345 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
\r
11346 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
\r
11347 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
\r
11348 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
\r
11349 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
\r
11350 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
\r
11351 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
\r
11352 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
\r
11353 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
\r
11354 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
\r
11355 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
\r
11356 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
\r
11357 #define RCC_APB1LPENR_RTCLPEN_Pos (10U)
\r
11358 #define RCC_APB1LPENR_RTCLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCLPEN_Pos) /*!< 0x00000400 */
\r
11359 #define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk
\r
11360 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
\r
11361 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
\r
11362 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
\r
11363 #define RCC_APB1LPENR_CAN3LPEN_Pos (13U)
\r
11364 #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x00002000 */
\r
11365 #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
\r
11366 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
\r
11367 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
\r
11368 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
\r
11369 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
\r
11370 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
\r
11371 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
\r
11372 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
\r
11373 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
\r
11374 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
\r
11375 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
\r
11376 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
\r
11377 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
\r
11378 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
\r
11379 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
\r
11380 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
\r
11381 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
\r
11382 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
\r
11383 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
\r
11384 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
\r
11385 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
\r
11386 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
\r
11387 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
\r
11388 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
\r
11389 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
\r
11390 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
\r
11391 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
\r
11392 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
\r
11393 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
\r
11394 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
\r
11395 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
\r
11396 #define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
\r
11397 #define RCC_APB1LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */
\r
11398 #define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
\r
11399 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
\r
11400 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
\r
11401 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
\r
11402 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
\r
11403 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
\r
11404 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
\r
11405 #define RCC_APB1LPENR_CECLPEN_Pos (27U)
\r
11406 #define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
\r
11407 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
\r
11408 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
\r
11409 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
\r
11410 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
\r
11411 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
\r
11412 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
\r
11413 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
\r
11414 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
\r
11415 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
\r
11416 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
\r
11417 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
\r
11418 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
\r
11419 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
\r
11421 /******************** Bit definition for RCC_APB2LPENR register *************/
\r
11422 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
\r
11423 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
\r
11424 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
\r
11425 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
\r
11426 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
\r
11427 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
\r
11428 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
\r
11429 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
\r
11430 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
\r
11431 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
\r
11432 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
\r
11433 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
\r
11434 #define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)
\r
11435 #define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
\r
11436 #define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk
\r
11437 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
\r
11438 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
\r
11439 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
\r
11440 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
\r
11441 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
\r
11442 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
\r
11443 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
\r
11444 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
\r
11445 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
\r
11446 #define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
\r
11447 #define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */
\r
11448 #define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
\r
11449 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
\r
11450 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
\r
11451 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
\r
11452 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
\r
11453 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
\r
11454 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
\r
11455 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
\r
11456 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
\r
11457 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
\r
11458 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
\r
11459 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
\r
11460 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
\r
11461 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
\r
11462 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
\r
11463 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
\r
11464 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
\r
11465 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
\r
11466 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
\r
11467 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
\r
11468 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
\r
11469 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
\r
11470 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
\r
11471 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
\r
11472 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
\r
11473 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
\r
11474 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
\r
11475 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
\r
11476 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
\r
11477 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
\r
11478 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
\r
11479 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
\r
11480 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
\r
11481 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
\r
11482 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U)
\r
11483 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x20000000 */
\r
11484 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
\r
11485 #define RCC_APB2LPENR_MDIOLPEN_Pos (30U)
\r
11486 #define RCC_APB2LPENR_MDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_MDIOLPEN_Pos) /*!< 0x40000000 */
\r
11487 #define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk
\r
11489 /******************** Bit definition for RCC_BDCR register ******************/
\r
11490 #define RCC_BDCR_LSEON_Pos (0U)
\r
11491 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
\r
11492 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
\r
11493 #define RCC_BDCR_LSERDY_Pos (1U)
\r
11494 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
\r
11495 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
\r
11496 #define RCC_BDCR_LSEBYP_Pos (2U)
\r
11497 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
\r
11498 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
\r
11499 #define RCC_BDCR_LSEDRV_Pos (3U)
\r
11500 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
\r
11501 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
\r
11502 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
\r
11503 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
\r
11504 #define RCC_BDCR_RTCSEL_Pos (8U)
\r
11505 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
\r
11506 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
\r
11507 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
\r
11508 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
\r
11509 #define RCC_BDCR_RTCEN_Pos (15U)
\r
11510 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
\r
11511 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
\r
11512 #define RCC_BDCR_BDRST_Pos (16U)
\r
11513 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
\r
11514 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
\r
11516 /******************** Bit definition for RCC_CSR register *******************/
\r
11517 #define RCC_CSR_LSION_Pos (0U)
\r
11518 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
\r
11519 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
\r
11520 #define RCC_CSR_LSIRDY_Pos (1U)
\r
11521 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
\r
11522 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
\r
11523 #define RCC_CSR_RMVF_Pos (24U)
\r
11524 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
\r
11525 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
\r
11526 #define RCC_CSR_BORRSTF_Pos (25U)
\r
11527 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
\r
11528 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
\r
11529 #define RCC_CSR_PINRSTF_Pos (26U)
\r
11530 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
\r
11531 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
\r
11532 #define RCC_CSR_PORRSTF_Pos (27U)
\r
11533 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
\r
11534 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
\r
11535 #define RCC_CSR_SFTRSTF_Pos (28U)
\r
11536 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
\r
11537 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
\r
11538 #define RCC_CSR_IWDGRSTF_Pos (29U)
\r
11539 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
\r
11540 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
\r
11541 #define RCC_CSR_WWDGRSTF_Pos (30U)
\r
11542 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
\r
11543 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
\r
11544 #define RCC_CSR_LPWRRSTF_Pos (31U)
\r
11545 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
\r
11546 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
\r
11548 /******************** Bit definition for RCC_SSCGR register *****************/
\r
11549 #define RCC_SSCGR_MODPER_Pos (0U)
\r
11550 #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
\r
11551 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
\r
11552 #define RCC_SSCGR_INCSTEP_Pos (13U)
\r
11553 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
\r
11554 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
\r
11555 #define RCC_SSCGR_SPREADSEL_Pos (30U)
\r
11556 #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
\r
11557 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
\r
11558 #define RCC_SSCGR_SSCGEN_Pos (31U)
\r
11559 #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
\r
11560 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
\r
11562 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
\r
11563 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
\r
11564 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
\r
11565 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
\r
11566 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
\r
11567 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
\r
11568 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
\r
11569 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
\r
11570 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
\r
11571 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
\r
11572 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
\r
11573 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
\r
11574 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
\r
11575 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
\r
11576 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
\r
11577 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
\r
11578 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
\r
11579 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
\r
11580 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
\r
11581 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
\r
11582 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
\r
11583 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
\r
11584 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
\r
11585 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
\r
11586 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
\r
11587 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
\r
11588 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
\r
11589 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
\r
11590 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
\r
11591 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
\r
11592 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
\r
11594 /******************** Bit definition for RCC_PLLSAICFGR register ************/
\r
11595 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
\r
11596 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
\r
11597 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
\r
11598 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
\r
11599 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
\r
11600 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
\r
11601 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
\r
11602 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
\r
11603 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
\r
11604 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
\r
11605 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
\r
11606 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
\r
11607 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
\r
11608 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
\r
11609 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
\r
11610 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
\r
11611 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
\r
11612 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
\r
11613 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
\r
11614 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
\r
11615 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
\r
11616 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
\r
11617 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
\r
11618 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
\r
11619 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
\r
11620 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
\r
11621 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
\r
11622 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
\r
11623 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
\r
11624 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
\r
11626 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
\r
11627 #define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
\r
11628 #define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
\r
11629 #define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
\r
11630 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
\r
11631 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
\r
11632 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
\r
11633 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
\r
11634 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
\r
11636 #define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
\r
11637 #define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
\r
11638 #define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
\r
11639 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
\r
11640 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
\r
11641 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
\r
11642 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
\r
11643 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
\r
11645 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
\r
11646 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
\r
11647 #define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
\r
11648 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
\r
11649 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
\r
11652 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
\r
11654 #define RCC_SAI1SEL_PLLSRC_SUPPORT
\r
11655 #define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
\r
11656 #define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */
\r
11657 #define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
\r
11658 #define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */
\r
11659 #define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
\r
11662 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
\r
11664 #define RCC_SAI2SEL_PLLSRC_SUPPORT
\r
11665 #define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
\r
11666 #define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */
\r
11667 #define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
\r
11668 #define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */
\r
11669 #define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */
\r
11671 #define RCC_DCKCFGR1_TIMPRE_Pos (24U)
\r
11672 #define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */
\r
11673 #define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
\r
11674 #define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U)
\r
11675 #define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_DFSDM1SEL_Pos) /*!< 0x02000000 */
\r
11676 #define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk
\r
11677 #define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U)
\r
11678 #define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_ADFSDM1SEL_Pos) /*!< 0x04000000 */
\r
11679 #define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk
\r
11681 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
\r
11682 #define RCC_DCKCFGR2_USART1SEL_Pos (0U)
\r
11683 #define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */
\r
11684 #define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
\r
11685 #define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */
\r
11686 #define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */
\r
11687 #define RCC_DCKCFGR2_USART2SEL_Pos (2U)
\r
11688 #define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */
\r
11689 #define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
\r
11690 #define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */
\r
11691 #define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */
\r
11692 #define RCC_DCKCFGR2_USART3SEL_Pos (4U)
\r
11693 #define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */
\r
11694 #define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
\r
11695 #define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */
\r
11696 #define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */
\r
11697 #define RCC_DCKCFGR2_UART4SEL_Pos (6U)
\r
11698 #define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */
\r
11699 #define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
\r
11700 #define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */
\r
11701 #define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */
\r
11702 #define RCC_DCKCFGR2_UART5SEL_Pos (8U)
\r
11703 #define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */
\r
11704 #define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
\r
11705 #define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */
\r
11706 #define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */
\r
11707 #define RCC_DCKCFGR2_USART6SEL_Pos (10U)
\r
11708 #define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */
\r
11709 #define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
\r
11710 #define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */
\r
11711 #define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */
\r
11712 #define RCC_DCKCFGR2_UART7SEL_Pos (12U)
\r
11713 #define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */
\r
11714 #define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
\r
11715 #define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */
\r
11716 #define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */
\r
11717 #define RCC_DCKCFGR2_UART8SEL_Pos (14U)
\r
11718 #define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */
\r
11719 #define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
\r
11720 #define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */
\r
11721 #define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */
\r
11722 #define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
\r
11723 #define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */
\r
11724 #define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
\r
11725 #define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */
\r
11726 #define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */
\r
11727 #define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
\r
11728 #define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */
\r
11729 #define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
\r
11730 #define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */
\r
11731 #define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */
\r
11732 #define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
\r
11733 #define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */
\r
11734 #define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
\r
11735 #define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */
\r
11736 #define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */
\r
11737 #define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
\r
11738 #define RCC_DCKCFGR2_I2C4SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00C00000 */
\r
11739 #define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
\r
11740 #define RCC_DCKCFGR2_I2C4SEL_0 (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00400000 */
\r
11741 #define RCC_DCKCFGR2_I2C4SEL_1 (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00800000 */
\r
11742 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
\r
11743 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */
\r
11744 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
\r
11745 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */
\r
11746 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */
\r
11747 #define RCC_DCKCFGR2_CECSEL_Pos (26U)
\r
11748 #define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
\r
11749 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
\r
11750 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
\r
11751 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
\r
11752 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
\r
11753 #define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
\r
11754 #define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */
\r
11755 #define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
\r
11756 #define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)
\r
11757 #define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC2SEL_Pos) /*!< 0x20000000 */
\r
11758 #define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk
\r
11760 /******************************************************************************/
\r
11764 /******************************************************************************/
\r
11765 /******************** Bits definition for RNG_CR register *******************/
\r
11766 #define RNG_CR_RNGEN_Pos (2U)
\r
11767 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
\r
11768 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
\r
11769 #define RNG_CR_IE_Pos (3U)
\r
11770 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
\r
11771 #define RNG_CR_IE RNG_CR_IE_Msk
\r
11773 /******************** Bits definition for RNG_SR register *******************/
\r
11774 #define RNG_SR_DRDY_Pos (0U)
\r
11775 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
\r
11776 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
\r
11777 #define RNG_SR_CECS_Pos (1U)
\r
11778 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
\r
11779 #define RNG_SR_CECS RNG_SR_CECS_Msk
\r
11780 #define RNG_SR_SECS_Pos (2U)
\r
11781 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
\r
11782 #define RNG_SR_SECS RNG_SR_SECS_Msk
\r
11783 #define RNG_SR_CEIS_Pos (5U)
\r
11784 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
\r
11785 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
\r
11786 #define RNG_SR_SEIS_Pos (6U)
\r
11787 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
\r
11788 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
\r
11790 /******************************************************************************/
\r
11792 /* Real-Time Clock (RTC) */
\r
11794 /******************************************************************************/
\r
11795 /******************** Bits definition for RTC_TR register *******************/
\r
11796 #define RTC_TR_PM_Pos (22U)
\r
11797 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
\r
11798 #define RTC_TR_PM RTC_TR_PM_Msk
\r
11799 #define RTC_TR_HT_Pos (20U)
\r
11800 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
\r
11801 #define RTC_TR_HT RTC_TR_HT_Msk
\r
11802 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
\r
11803 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
\r
11804 #define RTC_TR_HU_Pos (16U)
\r
11805 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
\r
11806 #define RTC_TR_HU RTC_TR_HU_Msk
\r
11807 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
\r
11808 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
\r
11809 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
\r
11810 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
\r
11811 #define RTC_TR_MNT_Pos (12U)
\r
11812 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
\r
11813 #define RTC_TR_MNT RTC_TR_MNT_Msk
\r
11814 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
\r
11815 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
\r
11816 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
\r
11817 #define RTC_TR_MNU_Pos (8U)
\r
11818 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
\r
11819 #define RTC_TR_MNU RTC_TR_MNU_Msk
\r
11820 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
\r
11821 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
\r
11822 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
\r
11823 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
\r
11824 #define RTC_TR_ST_Pos (4U)
\r
11825 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
\r
11826 #define RTC_TR_ST RTC_TR_ST_Msk
\r
11827 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
\r
11828 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
\r
11829 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
\r
11830 #define RTC_TR_SU_Pos (0U)
\r
11831 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
\r
11832 #define RTC_TR_SU RTC_TR_SU_Msk
\r
11833 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
\r
11834 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
\r
11835 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
\r
11836 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
\r
11838 /******************** Bits definition for RTC_DR register *******************/
\r
11839 #define RTC_DR_YT_Pos (20U)
\r
11840 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
\r
11841 #define RTC_DR_YT RTC_DR_YT_Msk
\r
11842 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
\r
11843 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
\r
11844 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
\r
11845 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
\r
11846 #define RTC_DR_YU_Pos (16U)
\r
11847 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
\r
11848 #define RTC_DR_YU RTC_DR_YU_Msk
\r
11849 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
\r
11850 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
\r
11851 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
\r
11852 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
\r
11853 #define RTC_DR_WDU_Pos (13U)
\r
11854 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
\r
11855 #define RTC_DR_WDU RTC_DR_WDU_Msk
\r
11856 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
\r
11857 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
\r
11858 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
\r
11859 #define RTC_DR_MT_Pos (12U)
\r
11860 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
\r
11861 #define RTC_DR_MT RTC_DR_MT_Msk
\r
11862 #define RTC_DR_MU_Pos (8U)
\r
11863 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
\r
11864 #define RTC_DR_MU RTC_DR_MU_Msk
\r
11865 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
\r
11866 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
\r
11867 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
\r
11868 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
\r
11869 #define RTC_DR_DT_Pos (4U)
\r
11870 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
\r
11871 #define RTC_DR_DT RTC_DR_DT_Msk
\r
11872 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
\r
11873 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
\r
11874 #define RTC_DR_DU_Pos (0U)
\r
11875 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
\r
11876 #define RTC_DR_DU RTC_DR_DU_Msk
\r
11877 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
\r
11878 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
\r
11879 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
\r
11880 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
\r
11882 /******************** Bits definition for RTC_CR register *******************/
\r
11883 #define RTC_CR_ITSE_Pos (24U)
\r
11884 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
\r
11885 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
\r
11886 #define RTC_CR_COE_Pos (23U)
\r
11887 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
\r
11888 #define RTC_CR_COE RTC_CR_COE_Msk
\r
11889 #define RTC_CR_OSEL_Pos (21U)
\r
11890 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
\r
11891 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
\r
11892 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
\r
11893 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
\r
11894 #define RTC_CR_POL_Pos (20U)
\r
11895 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
\r
11896 #define RTC_CR_POL RTC_CR_POL_Msk
\r
11897 #define RTC_CR_COSEL_Pos (19U)
\r
11898 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
\r
11899 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
\r
11900 #define RTC_CR_BKP_Pos (18U)
\r
11901 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
\r
11902 #define RTC_CR_BKP RTC_CR_BKP_Msk
\r
11903 #define RTC_CR_SUB1H_Pos (17U)
\r
11904 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
\r
11905 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
\r
11906 #define RTC_CR_ADD1H_Pos (16U)
\r
11907 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
\r
11908 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
\r
11909 #define RTC_CR_TSIE_Pos (15U)
\r
11910 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
\r
11911 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
\r
11912 #define RTC_CR_WUTIE_Pos (14U)
\r
11913 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
\r
11914 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
\r
11915 #define RTC_CR_ALRBIE_Pos (13U)
\r
11916 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
\r
11917 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
\r
11918 #define RTC_CR_ALRAIE_Pos (12U)
\r
11919 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
\r
11920 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
\r
11921 #define RTC_CR_TSE_Pos (11U)
\r
11922 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
\r
11923 #define RTC_CR_TSE RTC_CR_TSE_Msk
\r
11924 #define RTC_CR_WUTE_Pos (10U)
\r
11925 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
\r
11926 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
\r
11927 #define RTC_CR_ALRBE_Pos (9U)
\r
11928 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
\r
11929 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
\r
11930 #define RTC_CR_ALRAE_Pos (8U)
\r
11931 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
\r
11932 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
\r
11933 #define RTC_CR_FMT_Pos (6U)
\r
11934 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
\r
11935 #define RTC_CR_FMT RTC_CR_FMT_Msk
\r
11936 #define RTC_CR_BYPSHAD_Pos (5U)
\r
11937 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
\r
11938 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
\r
11939 #define RTC_CR_REFCKON_Pos (4U)
\r
11940 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
\r
11941 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
\r
11942 #define RTC_CR_TSEDGE_Pos (3U)
\r
11943 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
\r
11944 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
\r
11945 #define RTC_CR_WUCKSEL_Pos (0U)
\r
11946 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
\r
11947 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
\r
11948 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
\r
11949 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
\r
11950 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
\r
11952 /* Legacy define */
\r
11953 #define RTC_CR_BCK RTC_CR_BKP
\r
11955 /******************** Bits definition for RTC_ISR register ******************/
\r
11956 #define RTC_ISR_ITSF_Pos (17U)
\r
11957 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
\r
11958 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
\r
11959 #define RTC_ISR_RECALPF_Pos (16U)
\r
11960 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
\r
11961 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
\r
11962 #define RTC_ISR_TAMP3F_Pos (15U)
\r
11963 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
\r
11964 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
\r
11965 #define RTC_ISR_TAMP2F_Pos (14U)
\r
11966 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
\r
11967 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
\r
11968 #define RTC_ISR_TAMP1F_Pos (13U)
\r
11969 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
\r
11970 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
\r
11971 #define RTC_ISR_TSOVF_Pos (12U)
\r
11972 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
\r
11973 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
\r
11974 #define RTC_ISR_TSF_Pos (11U)
\r
11975 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
\r
11976 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
\r
11977 #define RTC_ISR_WUTF_Pos (10U)
\r
11978 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
\r
11979 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
\r
11980 #define RTC_ISR_ALRBF_Pos (9U)
\r
11981 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
\r
11982 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
\r
11983 #define RTC_ISR_ALRAF_Pos (8U)
\r
11984 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
\r
11985 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
\r
11986 #define RTC_ISR_INIT_Pos (7U)
\r
11987 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
\r
11988 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
\r
11989 #define RTC_ISR_INITF_Pos (6U)
\r
11990 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
\r
11991 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
\r
11992 #define RTC_ISR_RSF_Pos (5U)
\r
11993 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
\r
11994 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
\r
11995 #define RTC_ISR_INITS_Pos (4U)
\r
11996 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
\r
11997 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
\r
11998 #define RTC_ISR_SHPF_Pos (3U)
\r
11999 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
\r
12000 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
\r
12001 #define RTC_ISR_WUTWF_Pos (2U)
\r
12002 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
\r
12003 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
\r
12004 #define RTC_ISR_ALRBWF_Pos (1U)
\r
12005 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
\r
12006 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
\r
12007 #define RTC_ISR_ALRAWF_Pos (0U)
\r
12008 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
\r
12009 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
\r
12011 /******************** Bits definition for RTC_PRER register *****************/
\r
12012 #define RTC_PRER_PREDIV_A_Pos (16U)
\r
12013 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
\r
12014 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
\r
12015 #define RTC_PRER_PREDIV_S_Pos (0U)
\r
12016 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
\r
12017 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
\r
12019 /******************** Bits definition for RTC_WUTR register *****************/
\r
12020 #define RTC_WUTR_WUT_Pos (0U)
\r
12021 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
\r
12022 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
\r
12024 /******************** Bits definition for RTC_ALRMAR register ***************/
\r
12025 #define RTC_ALRMAR_MSK4_Pos (31U)
\r
12026 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
\r
12027 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
\r
12028 #define RTC_ALRMAR_WDSEL_Pos (30U)
\r
12029 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
\r
12030 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
\r
12031 #define RTC_ALRMAR_DT_Pos (28U)
\r
12032 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
\r
12033 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
\r
12034 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
\r
12035 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
\r
12036 #define RTC_ALRMAR_DU_Pos (24U)
\r
12037 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
\r
12038 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
\r
12039 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
\r
12040 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
\r
12041 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
\r
12042 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
\r
12043 #define RTC_ALRMAR_MSK3_Pos (23U)
\r
12044 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
\r
12045 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
\r
12046 #define RTC_ALRMAR_PM_Pos (22U)
\r
12047 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
\r
12048 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
\r
12049 #define RTC_ALRMAR_HT_Pos (20U)
\r
12050 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
\r
12051 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
\r
12052 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
\r
12053 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
\r
12054 #define RTC_ALRMAR_HU_Pos (16U)
\r
12055 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
\r
12056 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
\r
12057 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
\r
12058 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
\r
12059 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
\r
12060 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
\r
12061 #define RTC_ALRMAR_MSK2_Pos (15U)
\r
12062 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
\r
12063 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
\r
12064 #define RTC_ALRMAR_MNT_Pos (12U)
\r
12065 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
\r
12066 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
\r
12067 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
\r
12068 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
\r
12069 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
\r
12070 #define RTC_ALRMAR_MNU_Pos (8U)
\r
12071 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
\r
12072 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
\r
12073 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
\r
12074 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
\r
12075 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
\r
12076 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
\r
12077 #define RTC_ALRMAR_MSK1_Pos (7U)
\r
12078 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
\r
12079 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
\r
12080 #define RTC_ALRMAR_ST_Pos (4U)
\r
12081 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
\r
12082 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
\r
12083 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
\r
12084 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
\r
12085 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
\r
12086 #define RTC_ALRMAR_SU_Pos (0U)
\r
12087 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
\r
12088 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
\r
12089 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
\r
12090 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
\r
12091 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
\r
12092 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
\r
12094 /******************** Bits definition for RTC_ALRMBR register ***************/
\r
12095 #define RTC_ALRMBR_MSK4_Pos (31U)
\r
12096 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
\r
12097 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
\r
12098 #define RTC_ALRMBR_WDSEL_Pos (30U)
\r
12099 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
\r
12100 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
\r
12101 #define RTC_ALRMBR_DT_Pos (28U)
\r
12102 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
\r
12103 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
\r
12104 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
\r
12105 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
\r
12106 #define RTC_ALRMBR_DU_Pos (24U)
\r
12107 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
\r
12108 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
\r
12109 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
\r
12110 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
\r
12111 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
\r
12112 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
\r
12113 #define RTC_ALRMBR_MSK3_Pos (23U)
\r
12114 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
\r
12115 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
\r
12116 #define RTC_ALRMBR_PM_Pos (22U)
\r
12117 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
\r
12118 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
\r
12119 #define RTC_ALRMBR_HT_Pos (20U)
\r
12120 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
\r
12121 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
\r
12122 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
\r
12123 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
\r
12124 #define RTC_ALRMBR_HU_Pos (16U)
\r
12125 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
\r
12126 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
\r
12127 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
\r
12128 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
\r
12129 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
\r
12130 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
\r
12131 #define RTC_ALRMBR_MSK2_Pos (15U)
\r
12132 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
\r
12133 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
\r
12134 #define RTC_ALRMBR_MNT_Pos (12U)
\r
12135 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
\r
12136 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
\r
12137 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
\r
12138 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
\r
12139 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
\r
12140 #define RTC_ALRMBR_MNU_Pos (8U)
\r
12141 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
\r
12142 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
\r
12143 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
\r
12144 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
\r
12145 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
\r
12146 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
\r
12147 #define RTC_ALRMBR_MSK1_Pos (7U)
\r
12148 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
\r
12149 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
\r
12150 #define RTC_ALRMBR_ST_Pos (4U)
\r
12151 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
\r
12152 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
\r
12153 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
\r
12154 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
\r
12155 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
\r
12156 #define RTC_ALRMBR_SU_Pos (0U)
\r
12157 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
\r
12158 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
\r
12159 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
\r
12160 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
\r
12161 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
\r
12162 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
\r
12164 /******************** Bits definition for RTC_WPR register ******************/
\r
12165 #define RTC_WPR_KEY_Pos (0U)
\r
12166 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
\r
12167 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
\r
12169 /******************** Bits definition for RTC_SSR register ******************/
\r
12170 #define RTC_SSR_SS_Pos (0U)
\r
12171 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
\r
12172 #define RTC_SSR_SS RTC_SSR_SS_Msk
\r
12174 /******************** Bits definition for RTC_SHIFTR register ***************/
\r
12175 #define RTC_SHIFTR_SUBFS_Pos (0U)
\r
12176 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
\r
12177 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
\r
12178 #define RTC_SHIFTR_ADD1S_Pos (31U)
\r
12179 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
\r
12180 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
\r
12182 /******************** Bits definition for RTC_TSTR register *****************/
\r
12183 #define RTC_TSTR_PM_Pos (22U)
\r
12184 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
\r
12185 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
\r
12186 #define RTC_TSTR_HT_Pos (20U)
\r
12187 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
\r
12188 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
\r
12189 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
\r
12190 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
\r
12191 #define RTC_TSTR_HU_Pos (16U)
\r
12192 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
\r
12193 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
\r
12194 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
\r
12195 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
\r
12196 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
\r
12197 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
\r
12198 #define RTC_TSTR_MNT_Pos (12U)
\r
12199 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
\r
12200 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
\r
12201 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
\r
12202 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
\r
12203 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
\r
12204 #define RTC_TSTR_MNU_Pos (8U)
\r
12205 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
\r
12206 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
\r
12207 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
\r
12208 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
\r
12209 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
\r
12210 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
\r
12211 #define RTC_TSTR_ST_Pos (4U)
\r
12212 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
\r
12213 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
\r
12214 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
\r
12215 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
\r
12216 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
\r
12217 #define RTC_TSTR_SU_Pos (0U)
\r
12218 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
\r
12219 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
\r
12220 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
\r
12221 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
\r
12222 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
\r
12223 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
\r
12225 /******************** Bits definition for RTC_TSDR register *****************/
\r
12226 #define RTC_TSDR_WDU_Pos (13U)
\r
12227 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
\r
12228 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
\r
12229 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
\r
12230 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
\r
12231 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
\r
12232 #define RTC_TSDR_MT_Pos (12U)
\r
12233 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
\r
12234 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
\r
12235 #define RTC_TSDR_MU_Pos (8U)
\r
12236 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
\r
12237 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
\r
12238 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
\r
12239 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
\r
12240 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
\r
12241 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
\r
12242 #define RTC_TSDR_DT_Pos (4U)
\r
12243 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
\r
12244 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
\r
12245 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
\r
12246 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
\r
12247 #define RTC_TSDR_DU_Pos (0U)
\r
12248 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
\r
12249 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
\r
12250 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
\r
12251 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
\r
12252 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
\r
12253 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
\r
12255 /******************** Bits definition for RTC_TSSSR register ****************/
\r
12256 #define RTC_TSSSR_SS_Pos (0U)
\r
12257 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
\r
12258 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
\r
12260 /******************** Bits definition for RTC_CAL register *****************/
\r
12261 #define RTC_CALR_CALP_Pos (15U)
\r
12262 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
\r
12263 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
\r
12264 #define RTC_CALR_CALW8_Pos (14U)
\r
12265 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
\r
12266 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
\r
12267 #define RTC_CALR_CALW16_Pos (13U)
\r
12268 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
\r
12269 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
\r
12270 #define RTC_CALR_CALM_Pos (0U)
\r
12271 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
\r
12272 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
\r
12273 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
\r
12274 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
\r
12275 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
\r
12276 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
\r
12277 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
\r
12278 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
\r
12279 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
\r
12280 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
\r
12281 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
\r
12283 /******************** Bits definition for RTC_TAMPCR register ****************/
\r
12284 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
\r
12285 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
\r
12286 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
\r
12287 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
\r
12288 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
\r
12289 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
\r
12290 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
\r
12291 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
\r
12292 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
\r
12293 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
\r
12294 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
\r
12295 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
\r
12296 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
\r
12297 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
\r
12298 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
\r
12299 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
\r
12300 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
\r
12301 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
\r
12302 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
\r
12303 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
\r
12304 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
\r
12305 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
\r
12306 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
\r
12307 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
\r
12308 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
\r
12309 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
\r
12310 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
\r
12311 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
\r
12312 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
\r
12313 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
\r
12314 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
\r
12315 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
\r
12316 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
\r
12317 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
\r
12318 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
\r
12319 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
\r
12320 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
\r
12321 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
\r
12322 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
\r
12323 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
\r
12324 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
\r
12325 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
\r
12326 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
\r
12327 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
\r
12328 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
\r
12329 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
\r
12330 #define RTC_TAMPCR_TAMPTS_Pos (7U)
\r
12331 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
\r
12332 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
\r
12333 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
\r
12334 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
\r
12335 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
\r
12336 #define RTC_TAMPCR_TAMP3E_Pos (5U)
\r
12337 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
\r
12338 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
\r
12339 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
\r
12340 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
\r
12341 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
\r
12342 #define RTC_TAMPCR_TAMP2E_Pos (3U)
\r
12343 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
\r
12344 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
\r
12345 #define RTC_TAMPCR_TAMPIE_Pos (2U)
\r
12346 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
\r
12347 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
\r
12348 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
\r
12349 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
\r
12350 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
\r
12351 #define RTC_TAMPCR_TAMP1E_Pos (0U)
\r
12352 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
\r
12353 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
\r
12356 /******************** Bits definition for RTC_ALRMASSR register *************/
\r
12357 #define RTC_ALRMASSR_MASKSS_Pos (24U)
\r
12358 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
\r
12359 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
\r
12360 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
\r
12361 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
\r
12362 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
\r
12363 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
\r
12364 #define RTC_ALRMASSR_SS_Pos (0U)
\r
12365 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
\r
12366 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
\r
12368 /******************** Bits definition for RTC_ALRMBSSR register *************/
\r
12369 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
\r
12370 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
\r
12371 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
\r
12372 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
\r
12373 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
\r
12374 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
\r
12375 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
\r
12376 #define RTC_ALRMBSSR_SS_Pos (0U)
\r
12377 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
\r
12378 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
\r
12380 /******************** Bits definition for RTC_OR register ****************/
\r
12381 #define RTC_OR_TSINSEL_Pos (1U)
\r
12382 #define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */
\r
12383 #define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
\r
12384 #define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */
\r
12385 #define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */
\r
12386 #define RTC_OR_ALARMOUTTYPE_Pos (3U)
\r
12387 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */
\r
12388 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
\r
12389 /* Legacy defines*/
\r
12390 #define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
\r
12392 /******************** Bits definition for RTC_BKP0R register ****************/
\r
12393 #define RTC_BKP0R_Pos (0U)
\r
12394 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
\r
12395 #define RTC_BKP0R RTC_BKP0R_Msk
\r
12397 /******************** Bits definition for RTC_BKP1R register ****************/
\r
12398 #define RTC_BKP1R_Pos (0U)
\r
12399 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
\r
12400 #define RTC_BKP1R RTC_BKP1R_Msk
\r
12402 /******************** Bits definition for RTC_BKP2R register ****************/
\r
12403 #define RTC_BKP2R_Pos (0U)
\r
12404 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
\r
12405 #define RTC_BKP2R RTC_BKP2R_Msk
\r
12407 /******************** Bits definition for RTC_BKP3R register ****************/
\r
12408 #define RTC_BKP3R_Pos (0U)
\r
12409 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
\r
12410 #define RTC_BKP3R RTC_BKP3R_Msk
\r
12412 /******************** Bits definition for RTC_BKP4R register ****************/
\r
12413 #define RTC_BKP4R_Pos (0U)
\r
12414 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
\r
12415 #define RTC_BKP4R RTC_BKP4R_Msk
\r
12417 /******************** Bits definition for RTC_BKP5R register ****************/
\r
12418 #define RTC_BKP5R_Pos (0U)
\r
12419 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
\r
12420 #define RTC_BKP5R RTC_BKP5R_Msk
\r
12422 /******************** Bits definition for RTC_BKP6R register ****************/
\r
12423 #define RTC_BKP6R_Pos (0U)
\r
12424 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
\r
12425 #define RTC_BKP6R RTC_BKP6R_Msk
\r
12427 /******************** Bits definition for RTC_BKP7R register ****************/
\r
12428 #define RTC_BKP7R_Pos (0U)
\r
12429 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
\r
12430 #define RTC_BKP7R RTC_BKP7R_Msk
\r
12432 /******************** Bits definition for RTC_BKP8R register ****************/
\r
12433 #define RTC_BKP8R_Pos (0U)
\r
12434 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
\r
12435 #define RTC_BKP8R RTC_BKP8R_Msk
\r
12437 /******************** Bits definition for RTC_BKP9R register ****************/
\r
12438 #define RTC_BKP9R_Pos (0U)
\r
12439 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
\r
12440 #define RTC_BKP9R RTC_BKP9R_Msk
\r
12442 /******************** Bits definition for RTC_BKP10R register ***************/
\r
12443 #define RTC_BKP10R_Pos (0U)
\r
12444 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
\r
12445 #define RTC_BKP10R RTC_BKP10R_Msk
\r
12447 /******************** Bits definition for RTC_BKP11R register ***************/
\r
12448 #define RTC_BKP11R_Pos (0U)
\r
12449 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
\r
12450 #define RTC_BKP11R RTC_BKP11R_Msk
\r
12452 /******************** Bits definition for RTC_BKP12R register ***************/
\r
12453 #define RTC_BKP12R_Pos (0U)
\r
12454 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
\r
12455 #define RTC_BKP12R RTC_BKP12R_Msk
\r
12457 /******************** Bits definition for RTC_BKP13R register ***************/
\r
12458 #define RTC_BKP13R_Pos (0U)
\r
12459 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
\r
12460 #define RTC_BKP13R RTC_BKP13R_Msk
\r
12462 /******************** Bits definition for RTC_BKP14R register ***************/
\r
12463 #define RTC_BKP14R_Pos (0U)
\r
12464 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
\r
12465 #define RTC_BKP14R RTC_BKP14R_Msk
\r
12467 /******************** Bits definition for RTC_BKP15R register ***************/
\r
12468 #define RTC_BKP15R_Pos (0U)
\r
12469 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
\r
12470 #define RTC_BKP15R RTC_BKP15R_Msk
\r
12472 /******************** Bits definition for RTC_BKP16R register ***************/
\r
12473 #define RTC_BKP16R_Pos (0U)
\r
12474 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
\r
12475 #define RTC_BKP16R RTC_BKP16R_Msk
\r
12477 /******************** Bits definition for RTC_BKP17R register ***************/
\r
12478 #define RTC_BKP17R_Pos (0U)
\r
12479 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
\r
12480 #define RTC_BKP17R RTC_BKP17R_Msk
\r
12482 /******************** Bits definition for RTC_BKP18R register ***************/
\r
12483 #define RTC_BKP18R_Pos (0U)
\r
12484 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
\r
12485 #define RTC_BKP18R RTC_BKP18R_Msk
\r
12487 /******************** Bits definition for RTC_BKP19R register ***************/
\r
12488 #define RTC_BKP19R_Pos (0U)
\r
12489 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
\r
12490 #define RTC_BKP19R RTC_BKP19R_Msk
\r
12492 /******************** Bits definition for RTC_BKP20R register ***************/
\r
12493 #define RTC_BKP20R_Pos (0U)
\r
12494 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
\r
12495 #define RTC_BKP20R RTC_BKP20R_Msk
\r
12497 /******************** Bits definition for RTC_BKP21R register ***************/
\r
12498 #define RTC_BKP21R_Pos (0U)
\r
12499 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
\r
12500 #define RTC_BKP21R RTC_BKP21R_Msk
\r
12502 /******************** Bits definition for RTC_BKP22R register ***************/
\r
12503 #define RTC_BKP22R_Pos (0U)
\r
12504 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
\r
12505 #define RTC_BKP22R RTC_BKP22R_Msk
\r
12507 /******************** Bits definition for RTC_BKP23R register ***************/
\r
12508 #define RTC_BKP23R_Pos (0U)
\r
12509 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
\r
12510 #define RTC_BKP23R RTC_BKP23R_Msk
\r
12512 /******************** Bits definition for RTC_BKP24R register ***************/
\r
12513 #define RTC_BKP24R_Pos (0U)
\r
12514 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
\r
12515 #define RTC_BKP24R RTC_BKP24R_Msk
\r
12517 /******************** Bits definition for RTC_BKP25R register ***************/
\r
12518 #define RTC_BKP25R_Pos (0U)
\r
12519 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
\r
12520 #define RTC_BKP25R RTC_BKP25R_Msk
\r
12522 /******************** Bits definition for RTC_BKP26R register ***************/
\r
12523 #define RTC_BKP26R_Pos (0U)
\r
12524 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
\r
12525 #define RTC_BKP26R RTC_BKP26R_Msk
\r
12527 /******************** Bits definition for RTC_BKP27R register ***************/
\r
12528 #define RTC_BKP27R_Pos (0U)
\r
12529 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
\r
12530 #define RTC_BKP27R RTC_BKP27R_Msk
\r
12532 /******************** Bits definition for RTC_BKP28R register ***************/
\r
12533 #define RTC_BKP28R_Pos (0U)
\r
12534 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
\r
12535 #define RTC_BKP28R RTC_BKP28R_Msk
\r
12537 /******************** Bits definition for RTC_BKP29R register ***************/
\r
12538 #define RTC_BKP29R_Pos (0U)
\r
12539 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
\r
12540 #define RTC_BKP29R RTC_BKP29R_Msk
\r
12542 /******************** Bits definition for RTC_BKP30R register ***************/
\r
12543 #define RTC_BKP30R_Pos (0U)
\r
12544 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
\r
12545 #define RTC_BKP30R RTC_BKP30R_Msk
\r
12547 /******************** Bits definition for RTC_BKP31R register ***************/
\r
12548 #define RTC_BKP31R_Pos (0U)
\r
12549 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
\r
12550 #define RTC_BKP31R RTC_BKP31R_Msk
\r
12552 /******************** Number of backup registers ******************************/
\r
12553 #define RTC_BKP_NUMBER 0x00000020U
\r
12555 /******************************************************************************/
\r
12557 /* Serial Audio Interface */
\r
12559 /******************************************************************************/
\r
12560 /******************** Bit definition for SAI_GCR register *******************/
\r
12561 #define SAI_GCR_SYNCIN_Pos (0U)
\r
12562 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
\r
12563 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
\r
12564 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
\r
12565 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
\r
12567 #define SAI_GCR_SYNCOUT_Pos (4U)
\r
12568 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
\r
12569 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
\r
12570 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
\r
12571 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
\r
12573 /******************* Bit definition for SAI_xCR1 register *******************/
\r
12574 #define SAI_xCR1_MODE_Pos (0U)
\r
12575 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
\r
12576 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
\r
12577 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
\r
12578 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
\r
12580 #define SAI_xCR1_PRTCFG_Pos (2U)
\r
12581 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
\r
12582 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
\r
12583 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
\r
12584 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
\r
12586 #define SAI_xCR1_DS_Pos (5U)
\r
12587 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
\r
12588 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
\r
12589 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
\r
12590 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
\r
12591 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
\r
12593 #define SAI_xCR1_LSBFIRST_Pos (8U)
\r
12594 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
\r
12595 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
\r
12596 #define SAI_xCR1_CKSTR_Pos (9U)
\r
12597 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
\r
12598 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
\r
12600 #define SAI_xCR1_SYNCEN_Pos (10U)
\r
12601 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
\r
12602 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
\r
12603 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
\r
12604 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
\r
12606 #define SAI_xCR1_MONO_Pos (12U)
\r
12607 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
\r
12608 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
\r
12609 #define SAI_xCR1_OUTDRIV_Pos (13U)
\r
12610 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
\r
12611 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
\r
12612 #define SAI_xCR1_SAIEN_Pos (16U)
\r
12613 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
\r
12614 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
\r
12615 #define SAI_xCR1_DMAEN_Pos (17U)
\r
12616 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
\r
12617 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
\r
12618 #define SAI_xCR1_NODIV_Pos (19U)
\r
12619 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
\r
12620 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
\r
12622 #define SAI_xCR1_MCKDIV_Pos (20U)
\r
12623 #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
\r
12624 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
\r
12625 #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
\r
12626 #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
\r
12627 #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
\r
12628 #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
\r
12630 /******************* Bit definition for SAI_xCR2 register *******************/
\r
12631 #define SAI_xCR2_FTH_Pos (0U)
\r
12632 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
\r
12633 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
\r
12634 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
\r
12635 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
\r
12636 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
\r
12638 #define SAI_xCR2_FFLUSH_Pos (3U)
\r
12639 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
\r
12640 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
\r
12641 #define SAI_xCR2_TRIS_Pos (4U)
\r
12642 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
\r
12643 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
\r
12644 #define SAI_xCR2_MUTE_Pos (5U)
\r
12645 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
\r
12646 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
\r
12647 #define SAI_xCR2_MUTEVAL_Pos (6U)
\r
12648 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
\r
12649 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
\r
12651 #define SAI_xCR2_MUTECNT_Pos (7U)
\r
12652 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
\r
12653 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
\r
12654 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
\r
12655 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
\r
12656 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
\r
12657 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
\r
12658 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
\r
12659 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
\r
12661 #define SAI_xCR2_CPL_Pos (13U)
\r
12662 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
\r
12663 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
\r
12665 #define SAI_xCR2_COMP_Pos (14U)
\r
12666 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
\r
12667 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
\r
12668 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
\r
12669 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
\r
12671 /****************** Bit definition for SAI_xFRCR register *******************/
\r
12672 #define SAI_xFRCR_FRL_Pos (0U)
\r
12673 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
\r
12674 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
\r
12675 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
\r
12676 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
\r
12677 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
\r
12678 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
\r
12679 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
\r
12680 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
\r
12681 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
\r
12682 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
\r
12684 #define SAI_xFRCR_FSALL_Pos (8U)
\r
12685 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
\r
12686 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
\r
12687 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
\r
12688 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
\r
12689 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
\r
12690 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
\r
12691 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
\r
12692 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
\r
12693 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
\r
12695 #define SAI_xFRCR_FSDEF_Pos (16U)
\r
12696 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
\r
12697 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
\r
12698 #define SAI_xFRCR_FSPOL_Pos (17U)
\r
12699 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
\r
12700 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
\r
12701 #define SAI_xFRCR_FSOFF_Pos (18U)
\r
12702 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
\r
12703 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
\r
12705 /* Legacy define */
\r
12706 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
\r
12708 /****************** Bit definition for SAI_xSLOTR register *******************/
\r
12709 #define SAI_xSLOTR_FBOFF_Pos (0U)
\r
12710 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
\r
12711 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
\r
12712 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
\r
12713 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
\r
12714 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
\r
12715 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
\r
12716 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
\r
12718 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
\r
12719 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
\r
12720 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
\r
12721 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
\r
12722 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
\r
12724 #define SAI_xSLOTR_NBSLOT_Pos (8U)
\r
12725 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
\r
12726 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
\r
12727 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
\r
12728 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
\r
12729 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
\r
12730 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
\r
12732 #define SAI_xSLOTR_SLOTEN_Pos (16U)
\r
12733 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
\r
12734 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
\r
12736 /******************* Bit definition for SAI_xIMR register *******************/
\r
12737 #define SAI_xIMR_OVRUDRIE_Pos (0U)
\r
12738 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
\r
12739 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
\r
12740 #define SAI_xIMR_MUTEDETIE_Pos (1U)
\r
12741 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
\r
12742 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
\r
12743 #define SAI_xIMR_WCKCFGIE_Pos (2U)
\r
12744 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
\r
12745 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
\r
12746 #define SAI_xIMR_FREQIE_Pos (3U)
\r
12747 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
\r
12748 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
\r
12749 #define SAI_xIMR_CNRDYIE_Pos (4U)
\r
12750 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
\r
12751 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
\r
12752 #define SAI_xIMR_AFSDETIE_Pos (5U)
\r
12753 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
\r
12754 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
\r
12755 #define SAI_xIMR_LFSDETIE_Pos (6U)
\r
12756 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
\r
12757 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
\r
12759 /******************** Bit definition for SAI_xSR register *******************/
\r
12760 #define SAI_xSR_OVRUDR_Pos (0U)
\r
12761 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
\r
12762 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
\r
12763 #define SAI_xSR_MUTEDET_Pos (1U)
\r
12764 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
\r
12765 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
\r
12766 #define SAI_xSR_WCKCFG_Pos (2U)
\r
12767 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
\r
12768 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
\r
12769 #define SAI_xSR_FREQ_Pos (3U)
\r
12770 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
\r
12771 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
\r
12772 #define SAI_xSR_CNRDY_Pos (4U)
\r
12773 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
\r
12774 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
\r
12775 #define SAI_xSR_AFSDET_Pos (5U)
\r
12776 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
\r
12777 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
\r
12778 #define SAI_xSR_LFSDET_Pos (6U)
\r
12779 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
\r
12780 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
\r
12782 #define SAI_xSR_FLVL_Pos (16U)
\r
12783 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
\r
12784 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
\r
12785 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
\r
12786 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
\r
12787 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
\r
12789 /****************** Bit definition for SAI_xCLRFR register ******************/
\r
12790 #define SAI_xCLRFR_COVRUDR_Pos (0U)
\r
12791 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
\r
12792 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
\r
12793 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
\r
12794 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
\r
12795 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
\r
12796 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
\r
12797 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
\r
12798 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
\r
12799 #define SAI_xCLRFR_CFREQ_Pos (3U)
\r
12800 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
\r
12801 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
\r
12802 #define SAI_xCLRFR_CCNRDY_Pos (4U)
\r
12803 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
\r
12804 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
\r
12805 #define SAI_xCLRFR_CAFSDET_Pos (5U)
\r
12806 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
\r
12807 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
\r
12808 #define SAI_xCLRFR_CLFSDET_Pos (6U)
\r
12809 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
\r
12810 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
\r
12812 /****************** Bit definition for SAI_xDR register *********************/
\r
12813 #define SAI_xDR_DATA_Pos (0U)
\r
12814 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
\r
12815 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
\r
12817 /******************************************************************************/
\r
12819 /* SPDIF-RX Interface */
\r
12821 /******************************************************************************/
\r
12822 /******************** Bit definition for SPDIF_CR register *******************/
\r
12823 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
\r
12824 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
\r
12825 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
\r
12826 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
\r
12827 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
\r
12828 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
\r
12829 #define SPDIFRX_CR_RXSTEO_Pos (3U)
\r
12830 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
\r
12831 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
\r
12832 #define SPDIFRX_CR_DRFMT_Pos (4U)
\r
12833 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
\r
12834 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
\r
12835 #define SPDIFRX_CR_PMSK_Pos (6U)
\r
12836 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
\r
12837 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
\r
12838 #define SPDIFRX_CR_VMSK_Pos (7U)
\r
12839 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
\r
12840 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
\r
12841 #define SPDIFRX_CR_CUMSK_Pos (8U)
\r
12842 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
\r
12843 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
\r
12844 #define SPDIFRX_CR_PTMSK_Pos (9U)
\r
12845 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
\r
12846 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
\r
12847 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
\r
12848 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
\r
12849 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
\r
12850 #define SPDIFRX_CR_CHSEL_Pos (11U)
\r
12851 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
\r
12852 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
\r
12853 #define SPDIFRX_CR_NBTR_Pos (12U)
\r
12854 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
\r
12855 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
\r
12856 #define SPDIFRX_CR_WFA_Pos (14U)
\r
12857 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
\r
12858 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
\r
12859 #define SPDIFRX_CR_INSEL_Pos (16U)
\r
12860 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
\r
12861 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
\r
12863 /******************* Bit definition for SPDIFRX_IMR register *******************/
\r
12864 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
\r
12865 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
\r
12866 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
\r
12867 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
\r
12868 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
\r
12869 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
\r
12870 #define SPDIFRX_IMR_PERRIE_Pos (2U)
\r
12871 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
\r
12872 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
\r
12873 #define SPDIFRX_IMR_OVRIE_Pos (3U)
\r
12874 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
\r
12875 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
\r
12876 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
\r
12877 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
\r
12878 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
\r
12879 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
\r
12880 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
\r
12881 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
\r
12882 #define SPDIFRX_IMR_IFEIE_Pos (6U)
\r
12883 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
\r
12884 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
\r
12886 /******************* Bit definition for SPDIFRX_SR register *******************/
\r
12887 #define SPDIFRX_SR_RXNE_Pos (0U)
\r
12888 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
\r
12889 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
\r
12890 #define SPDIFRX_SR_CSRNE_Pos (1U)
\r
12891 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
\r
12892 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
\r
12893 #define SPDIFRX_SR_PERR_Pos (2U)
\r
12894 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
\r
12895 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
\r
12896 #define SPDIFRX_SR_OVR_Pos (3U)
\r
12897 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
\r
12898 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
\r
12899 #define SPDIFRX_SR_SBD_Pos (4U)
\r
12900 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
\r
12901 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
\r
12902 #define SPDIFRX_SR_SYNCD_Pos (5U)
\r
12903 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
\r
12904 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
\r
12905 #define SPDIFRX_SR_FERR_Pos (6U)
\r
12906 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
\r
12907 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
\r
12908 #define SPDIFRX_SR_SERR_Pos (7U)
\r
12909 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
\r
12910 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
\r
12911 #define SPDIFRX_SR_TERR_Pos (8U)
\r
12912 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
\r
12913 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
\r
12914 #define SPDIFRX_SR_WIDTH5_Pos (16U)
\r
12915 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
\r
12916 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
\r
12918 /******************* Bit definition for SPDIFRX_IFCR register *******************/
\r
12919 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
\r
12920 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
\r
12921 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
\r
12922 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
\r
12923 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
\r
12924 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
\r
12925 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
\r
12926 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
\r
12927 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
\r
12928 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
\r
12929 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
\r
12930 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
\r
12932 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
\r
12933 #define SPDIFRX_DR0_DR_Pos (0U)
\r
12934 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
\r
12935 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
\r
12936 #define SPDIFRX_DR0_PE_Pos (24U)
\r
12937 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
\r
12938 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
\r
12939 #define SPDIFRX_DR0_V_Pos (25U)
\r
12940 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
\r
12941 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
\r
12942 #define SPDIFRX_DR0_U_Pos (26U)
\r
12943 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
\r
12944 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
\r
12945 #define SPDIFRX_DR0_C_Pos (27U)
\r
12946 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
\r
12947 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
\r
12948 #define SPDIFRX_DR0_PT_Pos (28U)
\r
12949 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
\r
12950 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
\r
12952 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
\r
12953 #define SPDIFRX_DR1_DR_Pos (8U)
\r
12954 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
\r
12955 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
\r
12956 #define SPDIFRX_DR1_PT_Pos (4U)
\r
12957 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
\r
12958 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
\r
12959 #define SPDIFRX_DR1_C_Pos (3U)
\r
12960 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
\r
12961 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
\r
12962 #define SPDIFRX_DR1_U_Pos (2U)
\r
12963 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
\r
12964 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
\r
12965 #define SPDIFRX_DR1_V_Pos (1U)
\r
12966 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
\r
12967 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
\r
12968 #define SPDIFRX_DR1_PE_Pos (0U)
\r
12969 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
\r
12970 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
\r
12972 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
\r
12973 #define SPDIFRX_DR1_DRNL1_Pos (16U)
\r
12974 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
\r
12975 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
\r
12976 #define SPDIFRX_DR1_DRNL2_Pos (0U)
\r
12977 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
\r
12978 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
\r
12980 /******************* Bit definition for SPDIFRX_CSR register *******************/
\r
12981 #define SPDIFRX_CSR_USR_Pos (0U)
\r
12982 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
\r
12983 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
\r
12984 #define SPDIFRX_CSR_CS_Pos (16U)
\r
12985 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
\r
12986 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
\r
12987 #define SPDIFRX_CSR_SOB_Pos (24U)
\r
12988 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
\r
12989 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
\r
12991 /******************* Bit definition for SPDIFRX_DIR register *******************/
\r
12992 #define SPDIFRX_DIR_THI_Pos (0U)
\r
12993 #define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
\r
12994 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
\r
12995 #define SPDIFRX_DIR_TLO_Pos (16U)
\r
12996 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
\r
12997 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
\r
12999 /******************************************************************************/
\r
13001 /* SD host Interface */
\r
13003 /******************************************************************************/
\r
13004 /****************** Bit definition for SDMMC_POWER register ******************/
\r
13005 #define SDMMC_POWER_PWRCTRL_Pos (0U)
\r
13006 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
\r
13007 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
\r
13008 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */
\r
13009 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */
\r
13011 /****************** Bit definition for SDMMC_CLKCR register ******************/
\r
13012 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
\r
13013 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
\r
13014 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
\r
13015 #define SDMMC_CLKCR_CLKEN_Pos (8U)
\r
13016 #define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
\r
13017 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
\r
13018 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
\r
13019 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
\r
13020 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
\r
13021 #define SDMMC_CLKCR_BYPASS_Pos (10U)
\r
13022 #define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
\r
13023 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
\r
13025 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
\r
13026 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
\r
13027 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
\r
13028 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
\r
13029 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
\r
13031 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
\r
13032 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
\r
13033 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
\r
13034 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
\r
13035 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
\r
13036 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
\r
13038 /******************* Bit definition for SDMMC_ARG register *******************/
\r
13039 #define SDMMC_ARG_CMDARG_Pos (0U)
\r
13040 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
\r
13041 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
\r
13043 /******************* Bit definition for SDMMC_CMD register *******************/
\r
13044 #define SDMMC_CMD_CMDINDEX_Pos (0U)
\r
13045 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
\r
13046 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
\r
13048 #define SDMMC_CMD_WAITRESP_Pos (6U)
\r
13049 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
\r
13050 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
\r
13051 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */
\r
13052 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */
\r
13054 #define SDMMC_CMD_WAITINT_Pos (8U)
\r
13055 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
\r
13056 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
\r
13057 #define SDMMC_CMD_WAITPEND_Pos (9U)
\r
13058 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
\r
13059 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
\r
13060 #define SDMMC_CMD_CPSMEN_Pos (10U)
\r
13061 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
\r
13062 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
\r
13063 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
\r
13064 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
\r
13065 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
\r
13067 /***************** Bit definition for SDMMC_RESPCMD register *****************/
\r
13068 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
\r
13069 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
\r
13070 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
\r
13072 /****************** Bit definition for SDMMC_RESP0 register ******************/
\r
13073 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
\r
13074 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
\r
13075 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
\r
13077 /****************** Bit definition for SDMMC_RESP1 register ******************/
\r
13078 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
\r
13079 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
\r
13080 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
\r
13082 /****************** Bit definition for SDMMC_RESP2 register ******************/
\r
13083 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
\r
13084 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
\r
13085 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
\r
13087 /****************** Bit definition for SDMMC_RESP3 register ******************/
\r
13088 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
\r
13089 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
\r
13090 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
\r
13092 /****************** Bit definition for SDMMC_RESP4 register ******************/
\r
13093 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
\r
13094 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
\r
13095 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
\r
13097 /****************** Bit definition for SDMMC_DTIMER register *****************/
\r
13098 #define SDMMC_DTIMER_DATATIME_Pos (0U)
\r
13099 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
\r
13100 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
\r
13102 /****************** Bit definition for SDMMC_DLEN register *******************/
\r
13103 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
\r
13104 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
\r
13105 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
\r
13107 /****************** Bit definition for SDMMC_DCTRL register ******************/
\r
13108 #define SDMMC_DCTRL_DTEN_Pos (0U)
\r
13109 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
\r
13110 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
\r
13111 #define SDMMC_DCTRL_DTDIR_Pos (1U)
\r
13112 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
\r
13113 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
\r
13114 #define SDMMC_DCTRL_DTMODE_Pos (2U)
\r
13115 #define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
\r
13116 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
\r
13117 #define SDMMC_DCTRL_DMAEN_Pos (3U)
\r
13118 #define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
\r
13119 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
\r
13121 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
\r
13122 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
\r
13123 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
\r
13124 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
\r
13125 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
\r
13126 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
\r
13127 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
\r
13129 #define SDMMC_DCTRL_RWSTART_Pos (8U)
\r
13130 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
\r
13131 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
\r
13132 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
\r
13133 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
\r
13134 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
\r
13135 #define SDMMC_DCTRL_RWMOD_Pos (10U)
\r
13136 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
\r
13137 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
\r
13138 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
\r
13139 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
\r
13140 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
\r
13142 /****************** Bit definition for SDMMC_DCOUNT register *****************/
\r
13143 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
\r
13144 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
\r
13145 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
\r
13147 /****************** Bit definition for SDMMC_STA registe ********************/
\r
13148 #define SDMMC_STA_CCRCFAIL_Pos (0U)
\r
13149 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
\r
13150 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
\r
13151 #define SDMMC_STA_DCRCFAIL_Pos (1U)
\r
13152 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
\r
13153 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
\r
13154 #define SDMMC_STA_CTIMEOUT_Pos (2U)
\r
13155 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
\r
13156 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
\r
13157 #define SDMMC_STA_DTIMEOUT_Pos (3U)
\r
13158 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
\r
13159 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
\r
13160 #define SDMMC_STA_TXUNDERR_Pos (4U)
\r
13161 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
\r
13162 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
\r
13163 #define SDMMC_STA_RXOVERR_Pos (5U)
\r
13164 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
\r
13165 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
\r
13166 #define SDMMC_STA_CMDREND_Pos (6U)
\r
13167 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
\r
13168 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
\r
13169 #define SDMMC_STA_CMDSENT_Pos (7U)
\r
13170 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
\r
13171 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
\r
13172 #define SDMMC_STA_DATAEND_Pos (8U)
\r
13173 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
\r
13174 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
\r
13175 #define SDMMC_STA_DBCKEND_Pos (10U)
\r
13176 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
\r
13177 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
\r
13178 #define SDMMC_STA_CMDACT_Pos (11U)
\r
13179 #define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
\r
13180 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
\r
13181 #define SDMMC_STA_TXACT_Pos (12U)
\r
13182 #define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
\r
13183 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
\r
13184 #define SDMMC_STA_RXACT_Pos (13U)
\r
13185 #define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
\r
13186 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
\r
13187 #define SDMMC_STA_TXFIFOHE_Pos (14U)
\r
13188 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
\r
13189 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
\r
13190 #define SDMMC_STA_RXFIFOHF_Pos (15U)
\r
13191 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
\r
13192 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
\r
13193 #define SDMMC_STA_TXFIFOF_Pos (16U)
\r
13194 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
\r
13195 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
\r
13196 #define SDMMC_STA_RXFIFOF_Pos (17U)
\r
13197 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
\r
13198 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
\r
13199 #define SDMMC_STA_TXFIFOE_Pos (18U)
\r
13200 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
\r
13201 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
\r
13202 #define SDMMC_STA_RXFIFOE_Pos (19U)
\r
13203 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
\r
13204 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
\r
13205 #define SDMMC_STA_TXDAVL_Pos (20U)
\r
13206 #define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
\r
13207 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
\r
13208 #define SDMMC_STA_RXDAVL_Pos (21U)
\r
13209 #define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
\r
13210 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
\r
13211 #define SDMMC_STA_SDIOIT_Pos (22U)
\r
13212 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
\r
13213 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */
\r
13215 /******************* Bit definition for SDMMC_ICR register *******************/
\r
13216 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
\r
13217 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
\r
13218 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
\r
13219 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
\r
13220 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
\r
13221 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
\r
13222 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
\r
13223 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
\r
13224 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
\r
13225 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
\r
13226 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
\r
13227 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
\r
13228 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
\r
13229 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
\r
13230 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
\r
13231 #define SDMMC_ICR_RXOVERRC_Pos (5U)
\r
13232 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
\r
13233 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
\r
13234 #define SDMMC_ICR_CMDRENDC_Pos (6U)
\r
13235 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
\r
13236 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
\r
13237 #define SDMMC_ICR_CMDSENTC_Pos (7U)
\r
13238 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
\r
13239 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
\r
13240 #define SDMMC_ICR_DATAENDC_Pos (8U)
\r
13241 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
\r
13242 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
\r
13243 #define SDMMC_ICR_DBCKENDC_Pos (10U)
\r
13244 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
\r
13245 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
\r
13246 #define SDMMC_ICR_SDIOITC_Pos (22U)
\r
13247 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
\r
13248 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */
\r
13250 /****************** Bit definition for SDMMC_MASK register *******************/
\r
13251 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
\r
13252 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
\r
13253 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
\r
13254 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
\r
13255 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
\r
13256 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
\r
13257 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
\r
13258 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
\r
13259 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
\r
13260 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
\r
13261 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
\r
13262 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
\r
13263 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
\r
13264 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
\r
13265 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
\r
13266 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
\r
13267 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
\r
13268 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
\r
13269 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
\r
13270 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
\r
13271 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
\r
13272 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
\r
13273 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
\r
13274 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
\r
13275 #define SDMMC_MASK_DATAENDIE_Pos (8U)
\r
13276 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
\r
13277 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
\r
13278 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
\r
13279 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
\r
13280 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
\r
13281 #define SDMMC_MASK_CMDACTIE_Pos (11U)
\r
13282 #define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
\r
13283 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
\r
13284 #define SDMMC_MASK_TXACTIE_Pos (12U)
\r
13285 #define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
\r
13286 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
\r
13287 #define SDMMC_MASK_RXACTIE_Pos (13U)
\r
13288 #define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
\r
13289 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
\r
13290 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
\r
13291 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
\r
13292 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
\r
13293 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
\r
13294 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
\r
13295 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
\r
13296 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
\r
13297 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
\r
13298 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
\r
13299 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
\r
13300 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
\r
13301 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
\r
13302 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
\r
13303 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
\r
13304 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
\r
13305 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
\r
13306 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
\r
13307 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
\r
13308 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
\r
13309 #define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
\r
13310 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
\r
13311 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
\r
13312 #define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
\r
13313 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
\r
13314 #define SDMMC_MASK_SDIOITIE_Pos (22U)
\r
13315 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
\r
13316 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
\r
13318 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
\r
13319 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
\r
13320 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
\r
13321 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
\r
13323 /****************** Bit definition for SDMMC_FIFO register *******************/
\r
13324 #define SDMMC_FIFO_FIFODATA_Pos (0U)
\r
13325 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
\r
13326 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
\r
13328 /******************************************************************************/
\r
13330 /* Serial Peripheral Interface (SPI) */
\r
13332 /******************************************************************************/
\r
13333 /******************* Bit definition for SPI_CR1 register ********************/
\r
13334 #define SPI_CR1_CPHA_Pos (0U)
\r
13335 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
\r
13336 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
\r
13337 #define SPI_CR1_CPOL_Pos (1U)
\r
13338 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
\r
13339 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
\r
13340 #define SPI_CR1_MSTR_Pos (2U)
\r
13341 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
\r
13342 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
\r
13343 #define SPI_CR1_BR_Pos (3U)
\r
13344 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
\r
13345 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
\r
13346 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
\r
13347 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
\r
13348 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
\r
13349 #define SPI_CR1_SPE_Pos (6U)
\r
13350 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
\r
13351 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
\r
13352 #define SPI_CR1_LSBFIRST_Pos (7U)
\r
13353 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
\r
13354 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
\r
13355 #define SPI_CR1_SSI_Pos (8U)
\r
13356 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
\r
13357 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
\r
13358 #define SPI_CR1_SSM_Pos (9U)
\r
13359 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
\r
13360 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
\r
13361 #define SPI_CR1_RXONLY_Pos (10U)
\r
13362 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
\r
13363 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
\r
13364 #define SPI_CR1_CRCL_Pos (11U)
\r
13365 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
\r
13366 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
\r
13367 #define SPI_CR1_CRCNEXT_Pos (12U)
\r
13368 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
\r
13369 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
\r
13370 #define SPI_CR1_CRCEN_Pos (13U)
\r
13371 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
\r
13372 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
\r
13373 #define SPI_CR1_BIDIOE_Pos (14U)
\r
13374 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
\r
13375 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
\r
13376 #define SPI_CR1_BIDIMODE_Pos (15U)
\r
13377 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
\r
13378 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
\r
13380 /******************* Bit definition for SPI_CR2 register ********************/
\r
13381 #define SPI_CR2_RXDMAEN_Pos (0U)
\r
13382 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
\r
13383 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
\r
13384 #define SPI_CR2_TXDMAEN_Pos (1U)
\r
13385 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
\r
13386 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
\r
13387 #define SPI_CR2_SSOE_Pos (2U)
\r
13388 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
\r
13389 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
\r
13390 #define SPI_CR2_NSSP_Pos (3U)
\r
13391 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
\r
13392 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
\r
13393 #define SPI_CR2_FRF_Pos (4U)
\r
13394 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
\r
13395 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
\r
13396 #define SPI_CR2_ERRIE_Pos (5U)
\r
13397 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
\r
13398 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
\r
13399 #define SPI_CR2_RXNEIE_Pos (6U)
\r
13400 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
\r
13401 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
\r
13402 #define SPI_CR2_TXEIE_Pos (7U)
\r
13403 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
\r
13404 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
\r
13405 #define SPI_CR2_DS_Pos (8U)
\r
13406 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
\r
13407 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
\r
13408 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
\r
13409 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
\r
13410 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
\r
13411 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
\r
13412 #define SPI_CR2_FRXTH_Pos (12U)
\r
13413 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
\r
13414 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
\r
13415 #define SPI_CR2_LDMARX_Pos (13U)
\r
13416 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
\r
13417 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
\r
13418 #define SPI_CR2_LDMATX_Pos (14U)
\r
13419 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
\r
13420 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
\r
13422 /******************** Bit definition for SPI_SR register ********************/
\r
13423 #define SPI_SR_RXNE_Pos (0U)
\r
13424 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
\r
13425 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
\r
13426 #define SPI_SR_TXE_Pos (1U)
\r
13427 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
\r
13428 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
\r
13429 #define SPI_SR_CHSIDE_Pos (2U)
\r
13430 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
\r
13431 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
\r
13432 #define SPI_SR_UDR_Pos (3U)
\r
13433 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
\r
13434 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
\r
13435 #define SPI_SR_CRCERR_Pos (4U)
\r
13436 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
\r
13437 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
\r
13438 #define SPI_SR_MODF_Pos (5U)
\r
13439 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
\r
13440 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
\r
13441 #define SPI_SR_OVR_Pos (6U)
\r
13442 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
\r
13443 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
\r
13444 #define SPI_SR_BSY_Pos (7U)
\r
13445 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
\r
13446 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
\r
13447 #define SPI_SR_FRE_Pos (8U)
\r
13448 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
\r
13449 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
\r
13450 #define SPI_SR_FRLVL_Pos (9U)
\r
13451 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
\r
13452 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
\r
13453 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
\r
13454 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
\r
13455 #define SPI_SR_FTLVL_Pos (11U)
\r
13456 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
\r
13457 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
\r
13458 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
\r
13459 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
\r
13461 /******************** Bit definition for SPI_DR register ********************/
\r
13462 #define SPI_DR_DR_Pos (0U)
\r
13463 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
\r
13464 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
\r
13466 /******************* Bit definition for SPI_CRCPR register ******************/
\r
13467 #define SPI_CRCPR_CRCPOLY_Pos (0U)
\r
13468 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
\r
13469 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
\r
13471 /****************** Bit definition for SPI_RXCRCR register ******************/
\r
13472 #define SPI_RXCRCR_RXCRC_Pos (0U)
\r
13473 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
\r
13474 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
\r
13476 /****************** Bit definition for SPI_TXCRCR register ******************/
\r
13477 #define SPI_TXCRCR_TXCRC_Pos (0U)
\r
13478 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
\r
13479 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
\r
13481 /****************** Bit definition for SPI_I2SCFGR register *****************/
\r
13482 #define SPI_I2SCFGR_CHLEN_Pos (0U)
\r
13483 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
\r
13484 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
\r
13485 #define SPI_I2SCFGR_DATLEN_Pos (1U)
\r
13486 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
\r
13487 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
\r
13488 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
\r
13489 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
\r
13490 #define SPI_I2SCFGR_CKPOL_Pos (3U)
\r
13491 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
\r
13492 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
\r
13493 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
\r
13494 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
\r
13495 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
\r
13496 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
\r
13497 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
\r
13498 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
\r
13499 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
\r
13500 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
\r
13501 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
\r
13502 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
\r
13503 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
\r
13504 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
\r
13505 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
\r
13506 #define SPI_I2SCFGR_I2SE_Pos (10U)
\r
13507 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
\r
13508 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
\r
13509 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
\r
13510 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
\r
13511 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
\r
13512 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
\r
13513 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
\r
13514 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
\r
13516 /****************** Bit definition for SPI_I2SPR register *******************/
\r
13517 #define SPI_I2SPR_I2SDIV_Pos (0U)
\r
13518 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
\r
13519 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
\r
13520 #define SPI_I2SPR_ODD_Pos (8U)
\r
13521 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
\r
13522 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
\r
13523 #define SPI_I2SPR_MCKOE_Pos (9U)
\r
13524 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
\r
13525 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
\r
13528 /******************************************************************************/
\r
13532 /******************************************************************************/
\r
13533 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
\r
13534 #define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
\r
13535 #define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */
\r
13536 #define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */
\r
13538 #define SYSCFG_MEMRMP_SWP_FB_Pos (8U)
\r
13539 #define SYSCFG_MEMRMP_SWP_FB_Msk (0x1UL << SYSCFG_MEMRMP_SWP_FB_Pos) /*!< 0x00000100 */
\r
13540 #define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk /*!< User Flash Bank swap */
\r
13542 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
\r
13543 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
\r
13544 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */
\r
13545 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
\r
13546 #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
\r
13548 /****************** Bit definition for SYSCFG_PMC register ******************/
\r
13549 #define SYSCFG_PMC_I2C1_FMP_Pos (0U)
\r
13550 #define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
\r
13551 #define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
\r
13552 #define SYSCFG_PMC_I2C2_FMP_Pos (1U)
\r
13553 #define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
\r
13554 #define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
\r
13555 #define SYSCFG_PMC_I2C3_FMP_Pos (2U)
\r
13556 #define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
\r
13557 #define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
\r
13558 #define SYSCFG_PMC_I2C4_FMP_Pos (3U)
\r
13559 #define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
\r
13560 #define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
\r
13561 #define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
\r
13562 #define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
\r
13563 #define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
\r
13564 #define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
\r
13565 #define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
\r
13566 #define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
\r
13567 #define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
\r
13568 #define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
\r
13569 #define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
\r
13570 #define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
\r
13571 #define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
\r
13572 #define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
\r
13574 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
\r
13575 #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
\r
13576 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
\r
13577 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
\r
13578 #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
\r
13579 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
\r
13580 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
\r
13581 #define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
\r
13582 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
\r
13583 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
\r
13584 #define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
\r
13585 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
\r
13587 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
\r
13588 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
\r
13589 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
\r
13591 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
\r
13592 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
\r
13593 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
\r
13594 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
\r
13595 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
\r
13596 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
\r
13597 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
\r
13598 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
\r
13599 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
\r
13600 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
\r
13601 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
\r
13602 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
\r
13603 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
\r
13605 * @brief EXTI0 configuration
\r
13607 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
\r
13608 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
\r
13609 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
\r
13610 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
\r
13611 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
\r
13612 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
\r
13613 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
\r
13614 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
\r
13615 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
\r
13616 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
\r
13617 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
\r
13620 * @brief EXTI1 configuration
\r
13622 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
\r
13623 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
\r
13624 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
\r
13625 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
\r
13626 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
\r
13627 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
\r
13628 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
\r
13629 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
\r
13630 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
\r
13631 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
\r
13632 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
\r
13635 * @brief EXTI2 configuration
\r
13637 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
\r
13638 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
\r
13639 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
\r
13640 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
\r
13641 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
\r
13642 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
\r
13643 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
\r
13644 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
\r
13645 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
\r
13646 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
\r
13647 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
\r
13650 * @brief EXTI3 configuration
\r
13652 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
\r
13653 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
\r
13654 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
\r
13655 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
\r
13656 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
\r
13657 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
\r
13658 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
\r
13659 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
\r
13660 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
\r
13661 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
\r
13662 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
\r
13664 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
\r
13665 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
\r
13666 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
\r
13667 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
\r
13668 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
\r
13669 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
\r
13670 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
\r
13671 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
\r
13672 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
\r
13673 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
\r
13674 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
\r
13675 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
\r
13676 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
\r
13678 * @brief EXTI4 configuration
\r
13680 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
\r
13681 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
\r
13682 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
\r
13683 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
\r
13684 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
\r
13685 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
\r
13686 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
\r
13687 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
\r
13688 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
\r
13689 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
\r
13690 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
\r
13693 * @brief EXTI5 configuration
\r
13695 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
\r
13696 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
\r
13697 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
\r
13698 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
\r
13699 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
\r
13700 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
\r
13701 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
\r
13702 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
\r
13703 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
\r
13704 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
\r
13705 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
\r
13708 * @brief EXTI6 configuration
\r
13710 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
\r
13711 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
\r
13712 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
\r
13713 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
\r
13714 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
\r
13715 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
\r
13716 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
\r
13717 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
\r
13718 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
\r
13719 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
\r
13720 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
\r
13723 * @brief EXTI7 configuration
\r
13725 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
\r
13726 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
\r
13727 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
\r
13728 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
\r
13729 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
\r
13730 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
\r
13731 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
\r
13732 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
\r
13733 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
\r
13734 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
\r
13735 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
\r
13737 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
\r
13738 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
\r
13739 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
\r
13740 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
\r
13741 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
\r
13742 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
\r
13743 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
\r
13744 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
\r
13745 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
\r
13746 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
\r
13747 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
\r
13748 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
\r
13749 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
\r
13752 * @brief EXTI8 configuration
\r
13754 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
\r
13755 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
\r
13756 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
\r
13757 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
\r
13758 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
\r
13759 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
\r
13760 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
\r
13761 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
\r
13762 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
\r
13763 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
\r
13766 * @brief EXTI9 configuration
\r
13768 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
\r
13769 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
\r
13770 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
\r
13771 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
\r
13772 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
\r
13773 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
\r
13774 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
\r
13775 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
\r
13776 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
\r
13777 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
\r
13780 * @brief EXTI10 configuration
\r
13782 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
\r
13783 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
\r
13784 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
\r
13785 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
\r
13786 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
\r
13787 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
\r
13788 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
\r
13789 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
\r
13790 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
\r
13791 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
\r
13794 * @brief EXTI11 configuration
\r
13796 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
\r
13797 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
\r
13798 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
\r
13799 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
\r
13800 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
\r
13801 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
\r
13802 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
\r
13803 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
\r
13804 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
\r
13805 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
\r
13808 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
\r
13809 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
\r
13810 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
\r
13811 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
\r
13812 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
\r
13813 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
\r
13814 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
\r
13815 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
\r
13816 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
\r
13817 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
\r
13818 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
\r
13819 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
\r
13820 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
\r
13822 * @brief EXTI12 configuration
\r
13824 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
\r
13825 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
\r
13826 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
\r
13827 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
\r
13828 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
\r
13829 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
\r
13830 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
\r
13831 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
\r
13832 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
\r
13833 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
\r
13836 * @brief EXTI13 configuration
\r
13838 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
\r
13839 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
\r
13840 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
\r
13841 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
\r
13842 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
\r
13843 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
\r
13844 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
\r
13845 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
\r
13846 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
\r
13847 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
\r
13850 * @brief EXTI14 configuration
\r
13852 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
\r
13853 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
\r
13854 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
\r
13855 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
\r
13856 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
\r
13857 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
\r
13858 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
\r
13859 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
\r
13860 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
\r
13861 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
\r
13864 * @brief EXTI15 configuration
\r
13866 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
\r
13867 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
\r
13868 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
\r
13869 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
\r
13870 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
\r
13871 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
\r
13872 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
\r
13873 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
\r
13874 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
\r
13875 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
\r
13877 /****************** Bit definition for SYSCFG_CBR register ******************/
\r
13878 #define SYSCFG_CBR_CLL_Pos (0U)
\r
13879 #define SYSCFG_CBR_CLL_Msk (0x1UL << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */
\r
13880 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!<Core Lockup Lock */
\r
13881 #define SYSCFG_CBR_PVDL_Pos (2U)
\r
13882 #define SYSCFG_CBR_PVDL_Msk (0x1UL << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
\r
13883 #define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!<PVD Lock */
\r
13885 /****************** Bit definition for SYSCFG_CMPCR register ****************/
\r
13886 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
\r
13887 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
\r
13888 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */
\r
13889 #define SYSCFG_CMPCR_READY_Pos (8U)
\r
13890 #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
\r
13891 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */
\r
13893 /******************************************************************************/
\r
13897 /******************************************************************************/
\r
13899 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
\r
13901 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
\r
13902 /******************* Bit definition for TIM_CR1 register ********************/
\r
13903 #define TIM_CR1_CEN_Pos (0U)
\r
13904 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
\r
13905 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
\r
13906 #define TIM_CR1_UDIS_Pos (1U)
\r
13907 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
\r
13908 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
\r
13909 #define TIM_CR1_URS_Pos (2U)
\r
13910 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
\r
13911 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
\r
13912 #define TIM_CR1_OPM_Pos (3U)
\r
13913 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
\r
13914 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
\r
13915 #define TIM_CR1_DIR_Pos (4U)
\r
13916 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
\r
13917 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
\r
13919 #define TIM_CR1_CMS_Pos (5U)
\r
13920 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
\r
13921 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
\r
13922 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
\r
13923 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
\r
13925 #define TIM_CR1_ARPE_Pos (7U)
\r
13926 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
\r
13927 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
\r
13929 #define TIM_CR1_CKD_Pos (8U)
\r
13930 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
\r
13931 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
\r
13932 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
\r
13933 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
\r
13934 #define TIM_CR1_UIFREMAP_Pos (11U)
\r
13935 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
\r
13936 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */
\r
13938 /******************* Bit definition for TIM_CR2 register ********************/
\r
13939 #define TIM_CR2_CCPC_Pos (0U)
\r
13940 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
\r
13941 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
\r
13942 #define TIM_CR2_CCUS_Pos (2U)
\r
13943 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
\r
13944 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
\r
13945 #define TIM_CR2_CCDS_Pos (3U)
\r
13946 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
\r
13947 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
\r
13949 #define TIM_CR2_OIS5_Pos (16U)
\r
13950 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
\r
13951 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
\r
13952 #define TIM_CR2_OIS6_Pos (18U)
\r
13953 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
\r
13954 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
\r
13956 #define TIM_CR2_MMS_Pos (4U)
\r
13957 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
\r
13958 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
\r
13959 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
\r
13960 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
\r
13961 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
\r
13963 #define TIM_CR2_MMS2_Pos (20U)
\r
13964 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
\r
13965 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
\r
13966 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
\r
13967 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
\r
13968 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
\r
13969 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
\r
13971 #define TIM_CR2_TI1S_Pos (7U)
\r
13972 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
\r
13973 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
\r
13974 #define TIM_CR2_OIS1_Pos (8U)
\r
13975 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
\r
13976 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
\r
13977 #define TIM_CR2_OIS1N_Pos (9U)
\r
13978 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
\r
13979 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
\r
13980 #define TIM_CR2_OIS2_Pos (10U)
\r
13981 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
\r
13982 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
\r
13983 #define TIM_CR2_OIS2N_Pos (11U)
\r
13984 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
\r
13985 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
\r
13986 #define TIM_CR2_OIS3_Pos (12U)
\r
13987 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
\r
13988 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
\r
13989 #define TIM_CR2_OIS3N_Pos (13U)
\r
13990 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
\r
13991 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
\r
13992 #define TIM_CR2_OIS4_Pos (14U)
\r
13993 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
\r
13994 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
\r
13996 /******************* Bit definition for TIM_SMCR register *******************/
\r
13997 #define TIM_SMCR_SMS_Pos (0U)
\r
13998 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
\r
13999 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
\r
14000 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
\r
14001 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
\r
14002 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
\r
14003 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
\r
14005 #define TIM_SMCR_TS_Pos (4U)
\r
14006 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
\r
14007 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
\r
14008 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
\r
14009 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
\r
14010 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
\r
14012 #define TIM_SMCR_MSM_Pos (7U)
\r
14013 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
\r
14014 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
\r
14016 #define TIM_SMCR_ETF_Pos (8U)
\r
14017 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
\r
14018 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
\r
14019 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
\r
14020 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
\r
14021 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
\r
14022 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
\r
14024 #define TIM_SMCR_ETPS_Pos (12U)
\r
14025 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
\r
14026 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
\r
14027 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
\r
14028 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
\r
14030 #define TIM_SMCR_ECE_Pos (14U)
\r
14031 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
\r
14032 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
\r
14033 #define TIM_SMCR_ETP_Pos (15U)
\r
14034 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
\r
14035 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
\r
14037 /******************* Bit definition for TIM_DIER register *******************/
\r
14038 #define TIM_DIER_UIE_Pos (0U)
\r
14039 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
\r
14040 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
\r
14041 #define TIM_DIER_CC1IE_Pos (1U)
\r
14042 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
\r
14043 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
\r
14044 #define TIM_DIER_CC2IE_Pos (2U)
\r
14045 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
\r
14046 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
\r
14047 #define TIM_DIER_CC3IE_Pos (3U)
\r
14048 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
\r
14049 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
\r
14050 #define TIM_DIER_CC4IE_Pos (4U)
\r
14051 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
\r
14052 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
\r
14053 #define TIM_DIER_COMIE_Pos (5U)
\r
14054 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
\r
14055 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
\r
14056 #define TIM_DIER_TIE_Pos (6U)
\r
14057 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
\r
14058 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
\r
14059 #define TIM_DIER_BIE_Pos (7U)
\r
14060 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
\r
14061 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
\r
14062 #define TIM_DIER_UDE_Pos (8U)
\r
14063 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
\r
14064 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
\r
14065 #define TIM_DIER_CC1DE_Pos (9U)
\r
14066 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
\r
14067 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
\r
14068 #define TIM_DIER_CC2DE_Pos (10U)
\r
14069 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
\r
14070 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
\r
14071 #define TIM_DIER_CC3DE_Pos (11U)
\r
14072 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
\r
14073 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
\r
14074 #define TIM_DIER_CC4DE_Pos (12U)
\r
14075 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
\r
14076 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
\r
14077 #define TIM_DIER_COMDE_Pos (13U)
\r
14078 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
\r
14079 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
\r
14080 #define TIM_DIER_TDE_Pos (14U)
\r
14081 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
\r
14082 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
\r
14084 /******************** Bit definition for TIM_SR register ********************/
\r
14085 #define TIM_SR_UIF_Pos (0U)
\r
14086 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
\r
14087 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
\r
14088 #define TIM_SR_CC1IF_Pos (1U)
\r
14089 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
\r
14090 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
\r
14091 #define TIM_SR_CC2IF_Pos (2U)
\r
14092 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
\r
14093 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
\r
14094 #define TIM_SR_CC3IF_Pos (3U)
\r
14095 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
\r
14096 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
\r
14097 #define TIM_SR_CC4IF_Pos (4U)
\r
14098 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
\r
14099 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
\r
14100 #define TIM_SR_COMIF_Pos (5U)
\r
14101 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
\r
14102 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
\r
14103 #define TIM_SR_TIF_Pos (6U)
\r
14104 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
\r
14105 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
\r
14106 #define TIM_SR_BIF_Pos (7U)
\r
14107 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
\r
14108 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
\r
14109 #define TIM_SR_B2IF_Pos (8U)
\r
14110 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
\r
14111 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
\r
14112 #define TIM_SR_CC1OF_Pos (9U)
\r
14113 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
\r
14114 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
\r
14115 #define TIM_SR_CC2OF_Pos (10U)
\r
14116 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
\r
14117 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
\r
14118 #define TIM_SR_CC3OF_Pos (11U)
\r
14119 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
\r
14120 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
\r
14121 #define TIM_SR_CC4OF_Pos (12U)
\r
14122 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
\r
14123 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
\r
14124 #define TIM_SR_SBIF_Pos (13U)
\r
14125 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
\r
14126 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
\r
14127 #define TIM_SR_CC5IF_Pos (16U)
\r
14128 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
\r
14129 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
\r
14130 #define TIM_SR_CC6IF_Pos (17U)
\r
14131 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
\r
14132 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
\r
14134 /******************* Bit definition for TIM_EGR register ********************/
\r
14135 #define TIM_EGR_UG_Pos (0U)
\r
14136 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
\r
14137 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
\r
14138 #define TIM_EGR_CC1G_Pos (1U)
\r
14139 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
\r
14140 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
\r
14141 #define TIM_EGR_CC2G_Pos (2U)
\r
14142 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
\r
14143 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
\r
14144 #define TIM_EGR_CC3G_Pos (3U)
\r
14145 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
\r
14146 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
\r
14147 #define TIM_EGR_CC4G_Pos (4U)
\r
14148 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
\r
14149 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
\r
14150 #define TIM_EGR_COMG_Pos (5U)
\r
14151 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
\r
14152 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
\r
14153 #define TIM_EGR_TG_Pos (6U)
\r
14154 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
\r
14155 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
\r
14156 #define TIM_EGR_BG_Pos (7U)
\r
14157 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
\r
14158 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
\r
14159 #define TIM_EGR_B2G_Pos (8U)
\r
14160 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
\r
14161 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */
\r
14163 /****************** Bit definition for TIM_CCMR1 register *******************/
\r
14164 #define TIM_CCMR1_CC1S_Pos (0U)
\r
14165 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
\r
14166 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
\r
14167 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
\r
14168 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
\r
14170 #define TIM_CCMR1_OC1FE_Pos (2U)
\r
14171 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
\r
14172 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
\r
14173 #define TIM_CCMR1_OC1PE_Pos (3U)
\r
14174 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
\r
14175 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
\r
14177 #define TIM_CCMR1_OC1M_Pos (4U)
\r
14178 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
\r
14179 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
\r
14180 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
\r
14181 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
\r
14182 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
\r
14183 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
\r
14185 #define TIM_CCMR1_OC1CE_Pos (7U)
\r
14186 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
\r
14187 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
\r
14189 #define TIM_CCMR1_CC2S_Pos (8U)
\r
14190 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
\r
14191 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
\r
14192 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
\r
14193 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
\r
14195 #define TIM_CCMR1_OC2FE_Pos (10U)
\r
14196 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
\r
14197 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
\r
14198 #define TIM_CCMR1_OC2PE_Pos (11U)
\r
14199 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
\r
14200 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
\r
14202 #define TIM_CCMR1_OC2M_Pos (12U)
\r
14203 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
\r
14204 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
\r
14205 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
\r
14206 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
\r
14207 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
\r
14208 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
\r
14210 #define TIM_CCMR1_OC2CE_Pos (15U)
\r
14211 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
\r
14212 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
\r
14214 /*----------------------------------------------------------------------------*/
\r
14216 #define TIM_CCMR1_IC1PSC_Pos (2U)
\r
14217 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
\r
14218 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
\r
14219 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
\r
14220 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
\r
14222 #define TIM_CCMR1_IC1F_Pos (4U)
\r
14223 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
\r
14224 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
\r
14225 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
\r
14226 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
\r
14227 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
\r
14228 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
\r
14230 #define TIM_CCMR1_IC2PSC_Pos (10U)
\r
14231 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
\r
14232 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
\r
14233 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
\r
14234 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
\r
14236 #define TIM_CCMR1_IC2F_Pos (12U)
\r
14237 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
\r
14238 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
\r
14239 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
\r
14240 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
\r
14241 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
\r
14242 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
\r
14244 /****************** Bit definition for TIM_CCMR2 register *******************/
\r
14245 #define TIM_CCMR2_CC3S_Pos (0U)
\r
14246 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
\r
14247 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
\r
14248 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
\r
14249 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
\r
14251 #define TIM_CCMR2_OC3FE_Pos (2U)
\r
14252 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
\r
14253 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
\r
14254 #define TIM_CCMR2_OC3PE_Pos (3U)
\r
14255 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
\r
14256 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
\r
14258 #define TIM_CCMR2_OC3M_Pos (4U)
\r
14259 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
\r
14260 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
\r
14261 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
\r
14262 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
\r
14263 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
\r
14264 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
\r
14268 #define TIM_CCMR2_OC3CE_Pos (7U)
\r
14269 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
\r
14270 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
\r
14272 #define TIM_CCMR2_CC4S_Pos (8U)
\r
14273 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
\r
14274 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
\r
14275 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
\r
14276 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
\r
14278 #define TIM_CCMR2_OC4FE_Pos (10U)
\r
14279 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
\r
14280 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
\r
14281 #define TIM_CCMR2_OC4PE_Pos (11U)
\r
14282 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
\r
14283 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
\r
14285 #define TIM_CCMR2_OC4M_Pos (12U)
\r
14286 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
\r
14287 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
14288 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
\r
14289 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
\r
14290 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
\r
14291 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
\r
14293 #define TIM_CCMR2_OC4CE_Pos (15U)
\r
14294 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
\r
14295 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
\r
14297 /*----------------------------------------------------------------------------*/
\r
14299 #define TIM_CCMR2_IC3PSC_Pos (2U)
\r
14300 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
\r
14301 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
\r
14302 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
\r
14303 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
\r
14305 #define TIM_CCMR2_IC3F_Pos (4U)
\r
14306 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
\r
14307 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
\r
14308 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
\r
14309 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
\r
14310 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
\r
14311 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
\r
14313 #define TIM_CCMR2_IC4PSC_Pos (10U)
\r
14314 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
\r
14315 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
\r
14316 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
\r
14317 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
\r
14319 #define TIM_CCMR2_IC4F_Pos (12U)
\r
14320 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
\r
14321 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
\r
14322 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
\r
14323 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
\r
14324 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
\r
14325 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
\r
14327 /******************* Bit definition for TIM_CCER register *******************/
\r
14328 #define TIM_CCER_CC1E_Pos (0U)
\r
14329 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
\r
14330 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
\r
14331 #define TIM_CCER_CC1P_Pos (1U)
\r
14332 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
\r
14333 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
\r
14334 #define TIM_CCER_CC1NE_Pos (2U)
\r
14335 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
\r
14336 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
\r
14337 #define TIM_CCER_CC1NP_Pos (3U)
\r
14338 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
\r
14339 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
\r
14340 #define TIM_CCER_CC2E_Pos (4U)
\r
14341 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
\r
14342 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
\r
14343 #define TIM_CCER_CC2P_Pos (5U)
\r
14344 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
\r
14345 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
\r
14346 #define TIM_CCER_CC2NE_Pos (6U)
\r
14347 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
\r
14348 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
\r
14349 #define TIM_CCER_CC2NP_Pos (7U)
\r
14350 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
\r
14351 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
\r
14352 #define TIM_CCER_CC3E_Pos (8U)
\r
14353 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
\r
14354 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
\r
14355 #define TIM_CCER_CC3P_Pos (9U)
\r
14356 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
\r
14357 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
\r
14358 #define TIM_CCER_CC3NE_Pos (10U)
\r
14359 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
\r
14360 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
\r
14361 #define TIM_CCER_CC3NP_Pos (11U)
\r
14362 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
\r
14363 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
\r
14364 #define TIM_CCER_CC4E_Pos (12U)
\r
14365 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
\r
14366 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
\r
14367 #define TIM_CCER_CC4P_Pos (13U)
\r
14368 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
\r
14369 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
\r
14370 #define TIM_CCER_CC4NP_Pos (15U)
\r
14371 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
\r
14372 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
\r
14373 #define TIM_CCER_CC5E_Pos (16U)
\r
14374 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
\r
14375 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
\r
14376 #define TIM_CCER_CC5P_Pos (17U)
\r
14377 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
\r
14378 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
\r
14379 #define TIM_CCER_CC6E_Pos (20U)
\r
14380 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
\r
14381 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
\r
14382 #define TIM_CCER_CC6P_Pos (21U)
\r
14383 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
\r
14384 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
\r
14387 /******************* Bit definition for TIM_CNT register ********************/
\r
14388 #define TIM_CNT_CNT_Pos (0U)
\r
14389 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
\r
14390 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
\r
14391 #define TIM_CNT_UIFCPY_Pos (31U)
\r
14392 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
\r
14393 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
\r
14395 /******************* Bit definition for TIM_PSC register ********************/
\r
14396 #define TIM_PSC_PSC_Pos (0U)
\r
14397 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
\r
14398 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
\r
14400 /******************* Bit definition for TIM_ARR register ********************/
\r
14401 #define TIM_ARR_ARR_Pos (0U)
\r
14402 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
\r
14403 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
\r
14405 /******************* Bit definition for TIM_RCR register ********************/
\r
14406 #define TIM_RCR_REP_Pos (0U)
\r
14407 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
\r
14408 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
\r
14410 /******************* Bit definition for TIM_CCR1 register *******************/
\r
14411 #define TIM_CCR1_CCR1_Pos (0U)
\r
14412 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
\r
14413 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
\r
14415 /******************* Bit definition for TIM_CCR2 register *******************/
\r
14416 #define TIM_CCR2_CCR2_Pos (0U)
\r
14417 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
\r
14418 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
\r
14420 /******************* Bit definition for TIM_CCR3 register *******************/
\r
14421 #define TIM_CCR3_CCR3_Pos (0U)
\r
14422 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
\r
14423 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
\r
14425 /******************* Bit definition for TIM_CCR4 register *******************/
\r
14426 #define TIM_CCR4_CCR4_Pos (0U)
\r
14427 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
\r
14428 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
\r
14430 /******************* Bit definition for TIM_BDTR register *******************/
\r
14431 #define TIM_BDTR_DTG_Pos (0U)
\r
14432 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
\r
14433 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
\r
14434 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
\r
14435 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
\r
14436 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
\r
14437 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
\r
14438 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
\r
14439 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
\r
14440 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
\r
14441 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
\r
14443 #define TIM_BDTR_LOCK_Pos (8U)
\r
14444 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
\r
14445 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
\r
14446 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
\r
14447 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
\r
14449 #define TIM_BDTR_OSSI_Pos (10U)
\r
14450 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
\r
14451 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
\r
14452 #define TIM_BDTR_OSSR_Pos (11U)
\r
14453 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
\r
14454 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
\r
14455 #define TIM_BDTR_BKE_Pos (12U)
\r
14456 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
\r
14457 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
\r
14458 #define TIM_BDTR_BKP_Pos (13U)
\r
14459 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
\r
14460 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
\r
14461 #define TIM_BDTR_AOE_Pos (14U)
\r
14462 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
\r
14463 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
\r
14464 #define TIM_BDTR_MOE_Pos (15U)
\r
14465 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
\r
14466 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
\r
14467 #define TIM_BDTR_BKF_Pos (16U)
\r
14468 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
\r
14469 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
\r
14470 #define TIM_BDTR_BK2F_Pos (20U)
\r
14471 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
\r
14472 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
\r
14473 #define TIM_BDTR_BK2E_Pos (24U)
\r
14474 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
\r
14475 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
\r
14476 #define TIM_BDTR_BK2P_Pos (25U)
\r
14477 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
\r
14478 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
\r
14480 /******************* Bit definition for TIM_DCR register ********************/
\r
14481 #define TIM_DCR_DBA_Pos (0U)
\r
14482 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
\r
14483 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
\r
14484 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
\r
14485 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
\r
14486 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
\r
14487 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
\r
14488 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
\r
14490 #define TIM_DCR_DBL_Pos (8U)
\r
14491 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
\r
14492 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
\r
14493 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
\r
14494 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
\r
14495 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
\r
14496 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
\r
14497 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
\r
14499 /******************* Bit definition for TIM_DMAR register *******************/
\r
14500 #define TIM_DMAR_DMAB_Pos (0U)
\r
14501 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
\r
14502 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
\r
14504 /******************* Bit definition for TIM_OR regiter *********************/
\r
14505 #define TIM_OR_TI4_RMP_Pos (6U)
\r
14506 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
\r
14507 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
\r
14508 #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
\r
14509 #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
\r
14510 #define TIM_OR_ITR1_RMP_Pos (10U)
\r
14511 #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
\r
14512 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
\r
14513 #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
\r
14514 #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
\r
14516 /******************* Bit definition for TIM2_OR register *******************/
\r
14517 #define TIM2_OR_ITR1_RMP_Pos (10U)
\r
14518 #define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
\r
14519 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
\r
14520 #define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */
\r
14521 #define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */
\r
14523 /******************* Bit definition for TIM5_OR register *******************/
\r
14524 #define TIM5_OR_TI4_RMP_Pos (6U)
\r
14525 #define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
\r
14526 #define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */
\r
14527 #define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */
\r
14528 #define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */
\r
14530 /******************* Bit definition for TIM11_OR register *******************/
\r
14531 #define TIM11_OR_TI1_RMP_Pos (0U)
\r
14532 #define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */
\r
14533 #define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
\r
14534 #define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */
\r
14535 #define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */
\r
14537 /****************** Bit definition for TIM_CCMR3 register *******************/
\r
14538 #define TIM_CCMR3_OC5FE_Pos (2U)
\r
14539 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
\r
14540 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
\r
14541 #define TIM_CCMR3_OC5PE_Pos (3U)
\r
14542 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
\r
14543 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
\r
14545 #define TIM_CCMR3_OC5M_Pos (4U)
\r
14546 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
\r
14547 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
\r
14548 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
\r
14549 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
\r
14550 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
\r
14551 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
\r
14553 #define TIM_CCMR3_OC5CE_Pos (7U)
\r
14554 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
\r
14555 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
\r
14557 #define TIM_CCMR3_OC6FE_Pos (10U)
\r
14558 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
\r
14559 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
\r
14560 #define TIM_CCMR3_OC6PE_Pos (11U)
\r
14561 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
\r
14562 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
\r
14564 #define TIM_CCMR3_OC6M_Pos (12U)
\r
14565 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
\r
14566 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
14567 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
\r
14568 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
\r
14569 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
\r
14570 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
\r
14572 #define TIM_CCMR3_OC6CE_Pos (15U)
\r
14573 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
\r
14574 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
\r
14576 /******************* Bit definition for TIM_CCR5 register *******************/
\r
14577 #define TIM_CCR5_CCR5_Pos (0U)
\r
14578 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
\r
14579 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
\r
14580 #define TIM_CCR5_GC5C1_Pos (29U)
\r
14581 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
\r
14582 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
\r
14583 #define TIM_CCR5_GC5C2_Pos (30U)
\r
14584 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
\r
14585 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
\r
14586 #define TIM_CCR5_GC5C3_Pos (31U)
\r
14587 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
\r
14588 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
\r
14590 /******************* Bit definition for TIM_CCR6 register *******************/
\r
14591 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
\r
14593 /******************* Bit definition for TIM1_AF1 register *******************/
\r
14594 #define TIM1_AF1_BKINE_Pos (0U)
\r
14595 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
14596 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
\r
14597 #define TIM1_AF1_BKDF1BKE_Pos (8U)
\r
14598 #define TIM1_AF1_BKDF1BKE_Msk (0x1UL << TIM1_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
\r
14599 #define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
\r
14600 #define TIM1_AF1_BKINP_Pos (9U)
\r
14601 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
14602 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
\r
14604 /******************* Bit definition for TIM1_AF2 register *******************/
\r
14605 #define TIM1_AF2_BK2INE_Pos (0U)
\r
14606 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
\r
14607 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
\r
14608 #define TIM1_AF2_BK2DF1BKE_Pos (8U)
\r
14609 #define TIM1_AF2_BK2DF1BKE_Msk (0x1UL << TIM1_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
\r
14610 #define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
\r
14611 #define TIM1_AF2_BK2INP_Pos (9U)
\r
14612 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
\r
14613 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
\r
14615 /******************* Bit definition for TIM8_AF1 register *******************/
\r
14616 #define TIM8_AF1_BKINE_Pos (0U)
\r
14617 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
14618 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BRK BKIN input enable */
\r
14619 #define TIM8_AF1_BKDF1BKE_Pos (8U)
\r
14620 #define TIM8_AF1_BKDF1BKE_Msk (0x1UL << TIM8_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
\r
14621 #define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
\r
14622 #define TIM8_AF1_BKINP_Pos (9U)
\r
14623 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
14624 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
\r
14626 /******************* Bit definition for TIM8_AF2 register *******************/
\r
14627 #define TIM8_AF2_BK2INE_Pos (0U)
\r
14628 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
\r
14629 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
\r
14630 #define TIM8_AF2_BK2DF1BKE_Pos (8U)
\r
14631 #define TIM8_AF2_BK2DF1BKE_Msk (0x1UL << TIM8_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
\r
14632 #define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
\r
14633 #define TIM8_AF2_BK2INP_Pos (9U)
\r
14634 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
\r
14635 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
\r
14638 /******************************************************************************/
\r
14640 /* Low Power Timer (LPTIM) */
\r
14642 /******************************************************************************/
\r
14643 /****************** Bit definition for LPTIM_ISR register *******************/
\r
14644 #define LPTIM_ISR_CMPM_Pos (0U)
\r
14645 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
\r
14646 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
\r
14647 #define LPTIM_ISR_ARRM_Pos (1U)
\r
14648 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
\r
14649 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
\r
14650 #define LPTIM_ISR_EXTTRIG_Pos (2U)
\r
14651 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
\r
14652 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
\r
14653 #define LPTIM_ISR_CMPOK_Pos (3U)
\r
14654 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
\r
14655 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
\r
14656 #define LPTIM_ISR_ARROK_Pos (4U)
\r
14657 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
\r
14658 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
\r
14659 #define LPTIM_ISR_UP_Pos (5U)
\r
14660 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
\r
14661 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
\r
14662 #define LPTIM_ISR_DOWN_Pos (6U)
\r
14663 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
\r
14664 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
\r
14666 /****************** Bit definition for LPTIM_ICR register *******************/
\r
14667 #define LPTIM_ICR_CMPMCF_Pos (0U)
\r
14668 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
\r
14669 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
\r
14670 #define LPTIM_ICR_ARRMCF_Pos (1U)
\r
14671 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
\r
14672 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
\r
14673 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
\r
14674 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
\r
14675 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
\r
14676 #define LPTIM_ICR_CMPOKCF_Pos (3U)
\r
14677 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
\r
14678 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
\r
14679 #define LPTIM_ICR_ARROKCF_Pos (4U)
\r
14680 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
\r
14681 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
\r
14682 #define LPTIM_ICR_UPCF_Pos (5U)
\r
14683 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
\r
14684 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
\r
14685 #define LPTIM_ICR_DOWNCF_Pos (6U)
\r
14686 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
\r
14687 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
\r
14689 /****************** Bit definition for LPTIM_IER register *******************/
\r
14690 #define LPTIM_IER_CMPMIE_Pos (0U)
\r
14691 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
\r
14692 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
\r
14693 #define LPTIM_IER_ARRMIE_Pos (1U)
\r
14694 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
\r
14695 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
\r
14696 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
\r
14697 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
\r
14698 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
\r
14699 #define LPTIM_IER_CMPOKIE_Pos (3U)
\r
14700 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
\r
14701 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
\r
14702 #define LPTIM_IER_ARROKIE_Pos (4U)
\r
14703 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
\r
14704 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
\r
14705 #define LPTIM_IER_UPIE_Pos (5U)
\r
14706 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
\r
14707 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
\r
14708 #define LPTIM_IER_DOWNIE_Pos (6U)
\r
14709 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
\r
14710 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
\r
14712 /****************** Bit definition for LPTIM_CFGR register*******************/
\r
14713 #define LPTIM_CFGR_CKSEL_Pos (0U)
\r
14714 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
\r
14715 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
\r
14717 #define LPTIM_CFGR_CKPOL_Pos (1U)
\r
14718 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
\r
14719 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
\r
14720 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
\r
14721 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
\r
14723 #define LPTIM_CFGR_CKFLT_Pos (3U)
\r
14724 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
\r
14725 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
\r
14726 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
\r
14727 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
\r
14729 #define LPTIM_CFGR_TRGFLT_Pos (6U)
\r
14730 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
\r
14731 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
\r
14732 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
\r
14733 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
\r
14735 #define LPTIM_CFGR_PRESC_Pos (9U)
\r
14736 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
\r
14737 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
\r
14738 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
\r
14739 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
\r
14740 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
\r
14742 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
\r
14743 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
\r
14744 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
\r
14745 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
\r
14746 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
\r
14747 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
\r
14749 #define LPTIM_CFGR_TRIGEN_Pos (17U)
\r
14750 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
\r
14751 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
\r
14752 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
\r
14753 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
\r
14755 #define LPTIM_CFGR_TIMOUT_Pos (19U)
\r
14756 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
\r
14757 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
\r
14758 #define LPTIM_CFGR_WAVE_Pos (20U)
\r
14759 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
\r
14760 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
\r
14761 #define LPTIM_CFGR_WAVPOL_Pos (21U)
\r
14762 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
\r
14763 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
\r
14764 #define LPTIM_CFGR_PRELOAD_Pos (22U)
\r
14765 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
\r
14766 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
\r
14767 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
\r
14768 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
\r
14769 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
\r
14770 #define LPTIM_CFGR_ENC_Pos (24U)
\r
14771 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
\r
14772 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
\r
14774 /****************** Bit definition for LPTIM_CR register ********************/
\r
14775 #define LPTIM_CR_ENABLE_Pos (0U)
\r
14776 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
\r
14777 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
\r
14778 #define LPTIM_CR_SNGSTRT_Pos (1U)
\r
14779 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
\r
14780 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
\r
14781 #define LPTIM_CR_CNTSTRT_Pos (2U)
\r
14782 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
\r
14783 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
\r
14785 /****************** Bit definition for LPTIM_CMP register *******************/
\r
14786 #define LPTIM_CMP_CMP_Pos (0U)
\r
14787 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
\r
14788 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
\r
14790 /****************** Bit definition for LPTIM_ARR register *******************/
\r
14791 #define LPTIM_ARR_ARR_Pos (0U)
\r
14792 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
\r
14793 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
\r
14795 /****************** Bit definition for LPTIM_CNT register *******************/
\r
14796 #define LPTIM_CNT_CNT_Pos (0U)
\r
14797 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
\r
14798 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
\r
14799 /******************************************************************************/
\r
14801 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
\r
14803 /******************************************************************************/
\r
14804 /****************** Bit definition for USART_CR1 register *******************/
\r
14805 #define USART_CR1_UE_Pos (0U)
\r
14806 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
\r
14807 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
\r
14808 #define USART_CR1_RE_Pos (2U)
\r
14809 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
\r
14810 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
\r
14811 #define USART_CR1_TE_Pos (3U)
\r
14812 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
\r
14813 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
\r
14814 #define USART_CR1_IDLEIE_Pos (4U)
\r
14815 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
\r
14816 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
\r
14817 #define USART_CR1_RXNEIE_Pos (5U)
\r
14818 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
\r
14819 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
\r
14820 #define USART_CR1_TCIE_Pos (6U)
\r
14821 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
\r
14822 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
\r
14823 #define USART_CR1_TXEIE_Pos (7U)
\r
14824 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
\r
14825 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
\r
14826 #define USART_CR1_PEIE_Pos (8U)
\r
14827 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
\r
14828 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
\r
14829 #define USART_CR1_PS_Pos (9U)
\r
14830 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
\r
14831 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
\r
14832 #define USART_CR1_PCE_Pos (10U)
\r
14833 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
\r
14834 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
\r
14835 #define USART_CR1_WAKE_Pos (11U)
\r
14836 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
\r
14837 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
\r
14838 #define USART_CR1_M_Pos (12U)
\r
14839 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
\r
14840 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
\r
14841 #define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos) /*!< 0x00001000 */
\r
14842 #define USART_CR1_MME_Pos (13U)
\r
14843 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
\r
14844 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
\r
14845 #define USART_CR1_CMIE_Pos (14U)
\r
14846 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
\r
14847 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
\r
14848 #define USART_CR1_OVER8_Pos (15U)
\r
14849 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
\r
14850 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
\r
14851 #define USART_CR1_DEDT_Pos (16U)
\r
14852 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
\r
14853 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
\r
14854 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
\r
14855 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
\r
14856 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
\r
14857 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
\r
14858 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
\r
14859 #define USART_CR1_DEAT_Pos (21U)
\r
14860 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
\r
14861 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
\r
14862 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
\r
14863 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
\r
14864 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
\r
14865 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
\r
14866 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
\r
14867 #define USART_CR1_RTOIE_Pos (26U)
\r
14868 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
\r
14869 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
\r
14870 #define USART_CR1_EOBIE_Pos (27U)
\r
14871 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
\r
14872 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
\r
14873 #define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */
\r
14875 /* Legacy defines */
\r
14876 #define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */
\r
14877 #define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */
\r
14879 /****************** Bit definition for USART_CR2 register *******************/
\r
14880 #define USART_CR2_ADDM7_Pos (4U)
\r
14881 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
\r
14882 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
\r
14883 #define USART_CR2_LBDL_Pos (5U)
\r
14884 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
\r
14885 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
\r
14886 #define USART_CR2_LBDIE_Pos (6U)
\r
14887 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
\r
14888 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
\r
14889 #define USART_CR2_LBCL_Pos (8U)
\r
14890 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
\r
14891 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
\r
14892 #define USART_CR2_CPHA_Pos (9U)
\r
14893 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
\r
14894 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
\r
14895 #define USART_CR2_CPOL_Pos (10U)
\r
14896 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
\r
14897 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
\r
14898 #define USART_CR2_CLKEN_Pos (11U)
\r
14899 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
\r
14900 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
\r
14901 #define USART_CR2_STOP_Pos (12U)
\r
14902 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
\r
14903 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
\r
14904 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
\r
14905 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
\r
14906 #define USART_CR2_LINEN_Pos (14U)
\r
14907 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
\r
14908 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
\r
14909 #define USART_CR2_SWAP_Pos (15U)
\r
14910 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
\r
14911 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
\r
14912 #define USART_CR2_RXINV_Pos (16U)
\r
14913 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
\r
14914 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
\r
14915 #define USART_CR2_TXINV_Pos (17U)
\r
14916 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
\r
14917 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
\r
14918 #define USART_CR2_DATAINV_Pos (18U)
\r
14919 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
\r
14920 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
\r
14921 #define USART_CR2_MSBFIRST_Pos (19U)
\r
14922 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
\r
14923 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
\r
14924 #define USART_CR2_ABREN_Pos (20U)
\r
14925 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
\r
14926 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */
\r
14927 #define USART_CR2_ABRMODE_Pos (21U)
\r
14928 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
\r
14929 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
\r
14930 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
\r
14931 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
\r
14932 #define USART_CR2_RTOEN_Pos (23U)
\r
14933 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
\r
14934 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
\r
14935 #define USART_CR2_ADD_Pos (24U)
\r
14936 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
\r
14937 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
\r
14939 /****************** Bit definition for USART_CR3 register *******************/
\r
14940 #define USART_CR3_EIE_Pos (0U)
\r
14941 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
\r
14942 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
\r
14943 #define USART_CR3_IREN_Pos (1U)
\r
14944 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
\r
14945 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
\r
14946 #define USART_CR3_IRLP_Pos (2U)
\r
14947 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
\r
14948 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
\r
14949 #define USART_CR3_HDSEL_Pos (3U)
\r
14950 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
\r
14951 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
\r
14952 #define USART_CR3_NACK_Pos (4U)
\r
14953 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
\r
14954 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
\r
14955 #define USART_CR3_SCEN_Pos (5U)
\r
14956 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
\r
14957 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
\r
14958 #define USART_CR3_DMAR_Pos (6U)
\r
14959 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
\r
14960 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
\r
14961 #define USART_CR3_DMAT_Pos (7U)
\r
14962 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
\r
14963 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
\r
14964 #define USART_CR3_RTSE_Pos (8U)
\r
14965 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
\r
14966 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
\r
14967 #define USART_CR3_CTSE_Pos (9U)
\r
14968 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
\r
14969 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
\r
14970 #define USART_CR3_CTSIE_Pos (10U)
\r
14971 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
\r
14972 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
\r
14973 #define USART_CR3_ONEBIT_Pos (11U)
\r
14974 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
\r
14975 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
\r
14976 #define USART_CR3_OVRDIS_Pos (12U)
\r
14977 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
\r
14978 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
\r
14979 #define USART_CR3_DDRE_Pos (13U)
\r
14980 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
\r
14981 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
\r
14982 #define USART_CR3_DEM_Pos (14U)
\r
14983 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
\r
14984 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
\r
14985 #define USART_CR3_DEP_Pos (15U)
\r
14986 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
\r
14987 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
\r
14988 #define USART_CR3_SCARCNT_Pos (17U)
\r
14989 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
\r
14990 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
\r
14991 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
\r
14992 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
\r
14993 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
\r
14995 /****************** Bit definition for USART_BRR register *******************/
\r
14996 #define USART_BRR_DIV_FRACTION_Pos (0U)
\r
14997 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
\r
14998 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
\r
14999 #define USART_BRR_DIV_MANTISSA_Pos (4U)
\r
15000 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
\r
15001 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
\r
15003 /****************** Bit definition for USART_GTPR register ******************/
\r
15004 #define USART_GTPR_PSC_Pos (0U)
\r
15005 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
\r
15006 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
\r
15007 #define USART_GTPR_GT_Pos (8U)
\r
15008 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
\r
15009 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
\r
15012 /******************* Bit definition for USART_RTOR register *****************/
\r
15013 #define USART_RTOR_RTO_Pos (0U)
\r
15014 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
\r
15015 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
\r
15016 #define USART_RTOR_BLEN_Pos (24U)
\r
15017 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
\r
15018 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
\r
15020 /******************* Bit definition for USART_RQR register ******************/
\r
15021 #define USART_RQR_ABRRQ_Pos (0U)
\r
15022 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
\r
15023 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
\r
15024 #define USART_RQR_SBKRQ_Pos (1U)
\r
15025 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
\r
15026 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
\r
15027 #define USART_RQR_MMRQ_Pos (2U)
\r
15028 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
\r
15029 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
\r
15030 #define USART_RQR_RXFRQ_Pos (3U)
\r
15031 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
\r
15032 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
\r
15033 #define USART_RQR_TXFRQ_Pos (4U)
\r
15034 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
\r
15035 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
\r
15037 /******************* Bit definition for USART_ISR register ******************/
\r
15038 #define USART_ISR_PE_Pos (0U)
\r
15039 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
\r
15040 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
\r
15041 #define USART_ISR_FE_Pos (1U)
\r
15042 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
\r
15043 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
\r
15044 #define USART_ISR_NE_Pos (2U)
\r
15045 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
\r
15046 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
\r
15047 #define USART_ISR_ORE_Pos (3U)
\r
15048 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
\r
15049 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
\r
15050 #define USART_ISR_IDLE_Pos (4U)
\r
15051 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
\r
15052 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
\r
15053 #define USART_ISR_RXNE_Pos (5U)
\r
15054 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
\r
15055 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
\r
15056 #define USART_ISR_TC_Pos (6U)
\r
15057 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
\r
15058 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
\r
15059 #define USART_ISR_TXE_Pos (7U)
\r
15060 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
\r
15061 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
\r
15062 #define USART_ISR_LBDF_Pos (8U)
\r
15063 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
\r
15064 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
\r
15065 #define USART_ISR_CTSIF_Pos (9U)
\r
15066 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
\r
15067 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
\r
15068 #define USART_ISR_CTS_Pos (10U)
\r
15069 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
\r
15070 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
\r
15071 #define USART_ISR_RTOF_Pos (11U)
\r
15072 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
\r
15073 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
\r
15074 #define USART_ISR_EOBF_Pos (12U)
\r
15075 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
\r
15076 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
\r
15077 #define USART_ISR_ABRE_Pos (14U)
\r
15078 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
\r
15079 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
\r
15080 #define USART_ISR_ABRF_Pos (15U)
\r
15081 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
\r
15082 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
\r
15083 #define USART_ISR_BUSY_Pos (16U)
\r
15084 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
\r
15085 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
\r
15086 #define USART_ISR_CMF_Pos (17U)
\r
15087 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
\r
15088 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
\r
15089 #define USART_ISR_SBKF_Pos (18U)
\r
15090 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
\r
15091 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
\r
15092 #define USART_ISR_RWU_Pos (19U)
\r
15093 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
\r
15094 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
\r
15095 #define USART_ISR_TEACK_Pos (21U)
\r
15096 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
\r
15097 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
\r
15099 /******************* Bit definition for USART_ICR register ******************/
\r
15100 #define USART_ICR_PECF_Pos (0U)
\r
15101 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
\r
15102 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
\r
15103 #define USART_ICR_FECF_Pos (1U)
\r
15104 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
\r
15105 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
\r
15106 #define USART_ICR_NCF_Pos (2U)
\r
15107 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
\r
15108 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
\r
15109 #define USART_ICR_ORECF_Pos (3U)
\r
15110 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
\r
15111 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
\r
15112 #define USART_ICR_IDLECF_Pos (4U)
\r
15113 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
\r
15114 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
\r
15115 #define USART_ICR_TCCF_Pos (6U)
\r
15116 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
\r
15117 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
\r
15118 #define USART_ICR_LBDCF_Pos (8U)
\r
15119 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
\r
15120 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
\r
15121 #define USART_ICR_CTSCF_Pos (9U)
\r
15122 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
\r
15123 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
\r
15124 #define USART_ICR_RTOCF_Pos (11U)
\r
15125 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
\r
15126 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
\r
15127 #define USART_ICR_EOBCF_Pos (12U)
\r
15128 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
\r
15129 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
\r
15130 #define USART_ICR_CMCF_Pos (17U)
\r
15131 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
\r
15132 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
\r
15134 /******************* Bit definition for USART_RDR register ******************/
\r
15135 #define USART_RDR_RDR_Pos (0U)
\r
15136 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
\r
15137 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
\r
15139 /******************* Bit definition for USART_TDR register ******************/
\r
15140 #define USART_TDR_TDR_Pos (0U)
\r
15141 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
\r
15142 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
\r
15144 /******************************************************************************/
\r
15146 /* Window WATCHDOG */
\r
15148 /******************************************************************************/
\r
15149 /******************* Bit definition for WWDG_CR register ********************/
\r
15150 #define WWDG_CR_T_Pos (0U)
\r
15151 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
\r
15152 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
\r
15153 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
\r
15154 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
\r
15155 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
\r
15156 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
\r
15157 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
\r
15158 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
\r
15159 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
\r
15162 #define WWDG_CR_WDGA_Pos (7U)
\r
15163 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
\r
15164 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
\r
15166 /******************* Bit definition for WWDG_CFR register *******************/
\r
15167 #define WWDG_CFR_W_Pos (0U)
\r
15168 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
\r
15169 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
\r
15170 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
\r
15171 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
\r
15172 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
\r
15173 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
\r
15174 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
\r
15175 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
\r
15176 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
\r
15179 #define WWDG_CFR_WDGTB_Pos (7U)
\r
15180 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
\r
15181 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
\r
15182 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
\r
15183 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
\r
15186 #define WWDG_CFR_EWI_Pos (9U)
\r
15187 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
\r
15188 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
\r
15190 /******************* Bit definition for WWDG_SR register ********************/
\r
15191 #define WWDG_SR_EWIF_Pos (0U)
\r
15192 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
\r
15193 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
\r
15195 /******************************************************************************/
\r
15199 /******************************************************************************/
\r
15200 /******************** Bit definition for DBGMCU_IDCODE register *************/
\r
15201 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
\r
15202 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
\r
15203 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
\r
15204 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
\r
15205 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
\r
15206 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
\r
15208 /******************** Bit definition for DBGMCU_CR register *****************/
\r
15209 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
\r
15210 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
\r
15211 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
\r
15212 #define DBGMCU_CR_DBG_STOP_Pos (1U)
\r
15213 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
\r
15214 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
\r
15215 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
\r
15216 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
\r
15217 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
\r
15218 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
\r
15219 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
\r
15220 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
\r
15222 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
\r
15223 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
\r
15224 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
\r
15225 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
\r
15226 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
\r
15228 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
\r
15229 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
\r
15230 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
\r
15231 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
\r
15232 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
\r
15233 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
\r
15234 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
\r
15235 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
\r
15236 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
\r
15237 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
\r
15238 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
\r
15239 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
\r
15240 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
\r
15241 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
\r
15242 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
\r
15243 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
\r
15244 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
\r
15245 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
\r
15246 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
\r
15247 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
\r
15248 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
\r
15249 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
\r
15250 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
\r
15251 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
\r
15252 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
\r
15253 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
\r
15254 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
\r
15255 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
\r
15256 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
\r
15257 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
\r
15258 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
\r
15259 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
\r
15260 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
\r
15261 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
\r
15262 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
\r
15263 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
\r
15264 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
\r
15265 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
\r
15266 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
\r
15267 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
\r
15268 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U)
\r
15269 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x00002000 */
\r
15270 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
\r
15271 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
\r
15272 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
\r
15273 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
\r
15274 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
\r
15275 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
\r
15276 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
\r
15277 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
\r
15278 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
\r
15279 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
\r
15280 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
\r
15281 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
\r
15282 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
\r
15283 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
\r
15284 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
\r
15285 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
\r
15286 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
\r
15287 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
\r
15288 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
\r
15290 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
\r
15291 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
\r
15292 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
\r
15293 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
\r
15294 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
\r
15295 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
\r
15296 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
\r
15297 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
\r
15298 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
\r
15299 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
\r
15300 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
\r
15301 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
\r
15302 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
\r
15303 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
\r
15304 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
\r
15305 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
\r
15307 /******************************************************************************/
\r
15309 /* Ethernet MAC Registers bits definitions */
\r
15311 /******************************************************************************/
\r
15312 /* Bit definition for Ethernet MAC Control Register register */
\r
15313 #define ETH_MACCR_WD_Pos (23U)
\r
15314 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
\r
15315 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
\r
15316 #define ETH_MACCR_JD_Pos (22U)
\r
15317 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
\r
15318 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
\r
15319 #define ETH_MACCR_IFG_Pos (17U)
\r
15320 #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
\r
15321 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
\r
15322 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
\r
15323 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
\r
15324 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
\r
15325 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
\r
15326 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
\r
15327 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
\r
15328 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
\r
15329 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
\r
15330 #define ETH_MACCR_CSD_Pos (16U)
\r
15331 #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
\r
15332 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
\r
15333 #define ETH_MACCR_FES_Pos (14U)
\r
15334 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
\r
15335 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
\r
15336 #define ETH_MACCR_ROD_Pos (13U)
\r
15337 #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
\r
15338 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
\r
15339 #define ETH_MACCR_LM_Pos (12U)
\r
15340 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
\r
15341 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
\r
15342 #define ETH_MACCR_DM_Pos (11U)
\r
15343 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
\r
15344 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
\r
15345 #define ETH_MACCR_IPCO_Pos (10U)
\r
15346 #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
\r
15347 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
\r
15348 #define ETH_MACCR_RD_Pos (9U)
\r
15349 #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
\r
15350 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
\r
15351 #define ETH_MACCR_APCS_Pos (7U)
\r
15352 #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
\r
15353 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
\r
15354 #define ETH_MACCR_BL_Pos (5U)
\r
15355 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
\r
15356 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
\r
15357 a transmission attempt during retries after a collision: 0 =< r <2^k */
\r
15358 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
\r
15359 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
\r
15360 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
\r
15361 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
\r
15362 #define ETH_MACCR_DC_Pos (4U)
\r
15363 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
\r
15364 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
\r
15365 #define ETH_MACCR_TE_Pos (3U)
\r
15366 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
\r
15367 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
\r
15368 #define ETH_MACCR_RE_Pos (2U)
\r
15369 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
\r
15370 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
\r
15372 /* Bit definition for Ethernet MAC Frame Filter Register */
\r
15373 #define ETH_MACFFR_RA_Pos (31U)
\r
15374 #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
\r
15375 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
\r
15376 #define ETH_MACFFR_HPF_Pos (10U)
\r
15377 #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
\r
15378 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
\r
15379 #define ETH_MACFFR_SAF_Pos (9U)
\r
15380 #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
\r
15381 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
\r
15382 #define ETH_MACFFR_SAIF_Pos (8U)
\r
15383 #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
\r
15384 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
\r
15385 #define ETH_MACFFR_PCF_Pos (6U)
\r
15386 #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
\r
15387 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
\r
15388 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
\r
15389 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
\r
15390 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
\r
15391 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
\r
15392 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
\r
15393 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
\r
15394 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
\r
15395 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
\r
15396 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
\r
15397 #define ETH_MACFFR_BFD_Pos (5U)
\r
15398 #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
\r
15399 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
\r
15400 #define ETH_MACFFR_PAM_Pos (4U)
\r
15401 #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
\r
15402 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
\r
15403 #define ETH_MACFFR_DAIF_Pos (3U)
\r
15404 #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
\r
15405 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
\r
15406 #define ETH_MACFFR_HM_Pos (2U)
\r
15407 #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
\r
15408 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
\r
15409 #define ETH_MACFFR_HU_Pos (1U)
\r
15410 #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
\r
15411 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
\r
15412 #define ETH_MACFFR_PM_Pos (0U)
\r
15413 #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
\r
15414 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
\r
15416 /* Bit definition for Ethernet MAC Hash Table High Register */
\r
15417 #define ETH_MACHTHR_HTH_Pos (0U)
\r
15418 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
\r
15419 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
\r
15421 /* Bit definition for Ethernet MAC Hash Table Low Register */
\r
15422 #define ETH_MACHTLR_HTL_Pos (0U)
\r
15423 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
\r
15424 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
\r
15426 /* Bit definition for Ethernet MAC MII Address Register */
\r
15427 #define ETH_MACMIIAR_PA_Pos (11U)
\r
15428 #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
\r
15429 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
\r
15430 #define ETH_MACMIIAR_MR_Pos (6U)
\r
15431 #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
\r
15432 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
\r
15433 #define ETH_MACMIIAR_CR_Pos (2U)
\r
15434 #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
\r
15435 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
\r
15436 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
\r
15437 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
\r
15438 #define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
\r
15439 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
\r
15440 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
\r
15441 #define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
\r
15442 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
\r
15443 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
\r
15444 #define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
\r
15445 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
\r
15446 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
\r
15447 #define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
\r
15448 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
\r
15449 #define ETH_MACMIIAR_MW_Pos (1U)
\r
15450 #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
\r
15451 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
\r
15452 #define ETH_MACMIIAR_MB_Pos (0U)
\r
15453 #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
\r
15454 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
\r
15456 /* Bit definition for Ethernet MAC MII Data Register */
\r
15457 #define ETH_MACMIIDR_MD_Pos (0U)
\r
15458 #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
\r
15459 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
\r
15461 /* Bit definition for Ethernet MAC Flow Control Register */
\r
15462 #define ETH_MACFCR_PT_Pos (16U)
\r
15463 #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
\r
15464 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
\r
15465 #define ETH_MACFCR_ZQPD_Pos (7U)
\r
15466 #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
\r
15467 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
\r
15468 #define ETH_MACFCR_PLT_Pos (4U)
\r
15469 #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
\r
15470 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
\r
15471 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
\r
15472 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
\r
15473 #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
\r
15474 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
\r
15475 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
\r
15476 #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
\r
15477 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
\r
15478 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
\r
15479 #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
\r
15480 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
\r
15481 #define ETH_MACFCR_UPFD_Pos (3U)
\r
15482 #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
\r
15483 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
\r
15484 #define ETH_MACFCR_RFCE_Pos (2U)
\r
15485 #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
\r
15486 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
\r
15487 #define ETH_MACFCR_TFCE_Pos (1U)
\r
15488 #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
\r
15489 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
\r
15490 #define ETH_MACFCR_FCBBPA_Pos (0U)
\r
15491 #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
\r
15492 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
\r
15494 /* Bit definition for Ethernet MAC VLAN Tag Register */
\r
15495 #define ETH_MACVLANTR_VLANTC_Pos (16U)
\r
15496 #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
\r
15497 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
\r
15498 #define ETH_MACVLANTR_VLANTI_Pos (0U)
\r
15499 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
\r
15500 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
\r
15502 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
\r
15503 #define ETH_MACRWUFFR_D_Pos (0U)
\r
15504 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
\r
15505 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
\r
15506 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
\r
15507 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
\r
15508 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
\r
15509 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
\r
15510 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
\r
15511 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
\r
15512 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
\r
15513 RSVD - Filter1 Command - RSVD - Filter0 Command
\r
15514 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
\r
15515 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
\r
15516 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
\r
15518 /* Bit definition for Ethernet MAC PMT Control and Status Register */
\r
15519 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
\r
15520 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
\r
15521 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
\r
15522 #define ETH_MACPMTCSR_GU_Pos (9U)
\r
15523 #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
\r
15524 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
\r
15525 #define ETH_MACPMTCSR_WFR_Pos (6U)
\r
15526 #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
\r
15527 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
\r
15528 #define ETH_MACPMTCSR_MPR_Pos (5U)
\r
15529 #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
\r
15530 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
\r
15531 #define ETH_MACPMTCSR_WFE_Pos (2U)
\r
15532 #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
\r
15533 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
\r
15534 #define ETH_MACPMTCSR_MPE_Pos (1U)
\r
15535 #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
\r
15536 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
\r
15537 #define ETH_MACPMTCSR_PD_Pos (0U)
\r
15538 #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
\r
15539 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
\r
15541 /* Bit definition for Ethernet MAC debug Register */
\r
15542 #define ETH_MACDBGR_TFF_Pos (25U)
\r
15543 #define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
\r
15544 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
\r
15545 #define ETH_MACDBGR_TFNE_Pos (24U)
\r
15546 #define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
\r
15547 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
\r
15548 #define ETH_MACDBGR_TPWA_Pos (22U)
\r
15549 #define ETH_MACDBGR_TPWA_Msk (0x1UL << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
\r
15550 #define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
\r
15551 #define ETH_MACDBGR_TFRS_Pos (20U)
\r
15552 #define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
\r
15553 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
\r
15554 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
\r
15555 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
\r
15556 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
\r
15557 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
\r
15558 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
\r
15559 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
\r
15560 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
\r
15561 #define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
\r
15562 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
\r
15563 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
\r
15564 #define ETH_MACDBGR_MTP_Pos (19U)
\r
15565 #define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
\r
15566 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
\r
15567 #define ETH_MACDBGR_MTFCS_Pos (17U)
\r
15568 #define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
\r
15569 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
\r
15570 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
\r
15571 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
\r
15572 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
\r
15573 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
\r
15574 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
\r
15575 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
\r
15576 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
\r
15577 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
\r
15578 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
\r
15579 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
\r
15580 #define ETH_MACDBGR_MMTEA_Pos (16U)
\r
15581 #define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
\r
15582 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
\r
15583 #define ETH_MACDBGR_RFFL_Pos (8U)
\r
15584 #define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
\r
15585 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
\r
15586 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
\r
15587 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
\r
15588 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
\r
15589 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
\r
15590 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
\r
15591 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
\r
15592 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
\r
15593 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
\r
15594 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
\r
15595 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
\r
15596 #define ETH_MACDBGR_RFRCS_Pos (5U)
\r
15597 #define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
\r
15598 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
\r
15599 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
\r
15600 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
\r
15601 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
\r
15602 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
\r
15603 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
\r
15604 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
\r
15605 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
\r
15606 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
\r
15607 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
\r
15608 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
\r
15609 #define ETH_MACDBGR_RFWRA_Pos (4U)
\r
15610 #define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
\r
15611 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
\r
15612 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
\r
15613 #define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
\r
15614 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
\r
15615 #define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
\r
15616 #define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
\r
15617 #define ETH_MACDBGR_MMRPEA_Pos (0U)
\r
15618 #define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
\r
15619 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
\r
15621 /* Bit definition for Ethernet MAC Status Register */
\r
15622 #define ETH_MACSR_TSTS_Pos (9U)
\r
15623 #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
\r
15624 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
\r
15625 #define ETH_MACSR_MMCTS_Pos (6U)
\r
15626 #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
\r
15627 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
\r
15628 #define ETH_MACSR_MMMCRS_Pos (5U)
\r
15629 #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
\r
15630 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
\r
15631 #define ETH_MACSR_MMCS_Pos (4U)
\r
15632 #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
\r
15633 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
\r
15634 #define ETH_MACSR_PMTS_Pos (3U)
\r
15635 #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
\r
15636 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
\r
15638 /* Bit definition for Ethernet MAC Interrupt Mask Register */
\r
15639 #define ETH_MACIMR_TSTIM_Pos (9U)
\r
15640 #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
\r
15641 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
\r
15642 #define ETH_MACIMR_PMTIM_Pos (3U)
\r
15643 #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
\r
15644 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
\r
15646 /* Bit definition for Ethernet MAC Address0 High Register */
\r
15647 #define ETH_MACA0HR_MACA0H_Pos (0U)
\r
15648 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
\r
15649 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
\r
15651 /* Bit definition for Ethernet MAC Address0 Low Register */
\r
15652 #define ETH_MACA0LR_MACA0L_Pos (0U)
\r
15653 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
\r
15654 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
\r
15656 /* Bit definition for Ethernet MAC Address1 High Register */
\r
15657 #define ETH_MACA1HR_AE_Pos (31U)
\r
15658 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
\r
15659 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
\r
15660 #define ETH_MACA1HR_SA_Pos (30U)
\r
15661 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
\r
15662 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
\r
15663 #define ETH_MACA1HR_MBC_Pos (24U)
\r
15664 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
\r
15665 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
\r
15666 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
\r
15667 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
\r
15668 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
\r
15669 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
\r
15670 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
\r
15671 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
\r
15672 #define ETH_MACA1HR_MACA1H_Pos (0U)
\r
15673 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
\r
15674 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
\r
15676 /* Bit definition for Ethernet MAC Address1 Low Register */
\r
15677 #define ETH_MACA1LR_MACA1L_Pos (0U)
\r
15678 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
\r
15679 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
\r
15681 /* Bit definition for Ethernet MAC Address2 High Register */
\r
15682 #define ETH_MACA2HR_AE_Pos (31U)
\r
15683 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
\r
15684 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
\r
15685 #define ETH_MACA2HR_SA_Pos (30U)
\r
15686 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
\r
15687 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
\r
15688 #define ETH_MACA2HR_MBC_Pos (24U)
\r
15689 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
\r
15690 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
\r
15691 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
\r
15692 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
\r
15693 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
\r
15694 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
\r
15695 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
\r
15696 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
\r
15697 #define ETH_MACA2HR_MACA2H_Pos (0U)
\r
15698 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
\r
15699 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
\r
15701 /* Bit definition for Ethernet MAC Address2 Low Register */
\r
15702 #define ETH_MACA2LR_MACA2L_Pos (0U)
\r
15703 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
\r
15704 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
\r
15706 /* Bit definition for Ethernet MAC Address3 High Register */
\r
15707 #define ETH_MACA3HR_AE_Pos (31U)
\r
15708 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
\r
15709 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
\r
15710 #define ETH_MACA3HR_SA_Pos (30U)
\r
15711 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
\r
15712 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
\r
15713 #define ETH_MACA3HR_MBC_Pos (24U)
\r
15714 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
\r
15715 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
\r
15716 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
\r
15717 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
\r
15718 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
\r
15719 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
\r
15720 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
\r
15721 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
\r
15722 #define ETH_MACA3HR_MACA3H_Pos (0U)
\r
15723 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
\r
15724 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
\r
15726 /* Bit definition for Ethernet MAC Address3 Low Register */
\r
15727 #define ETH_MACA3LR_MACA3L_Pos (0U)
\r
15728 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
\r
15729 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
\r
15731 /******************************************************************************/
\r
15732 /* Ethernet MMC Registers bits definition */
\r
15733 /******************************************************************************/
\r
15735 /* Bit definition for Ethernet MMC Contol Register */
\r
15736 #define ETH_MMCCR_MCFHP_Pos (5U)
\r
15737 #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
\r
15738 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
\r
15739 #define ETH_MMCCR_MCP_Pos (4U)
\r
15740 #define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
\r
15741 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
\r
15742 #define ETH_MMCCR_MCF_Pos (3U)
\r
15743 #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
\r
15744 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
\r
15745 #define ETH_MMCCR_ROR_Pos (2U)
\r
15746 #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
\r
15747 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
\r
15748 #define ETH_MMCCR_CSR_Pos (1U)
\r
15749 #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
\r
15750 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
\r
15751 #define ETH_MMCCR_CR_Pos (0U)
\r
15752 #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
\r
15753 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
\r
15755 /* Bit definition for Ethernet MMC Receive Interrupt Register */
\r
15756 #define ETH_MMCRIR_RGUFS_Pos (17U)
\r
15757 #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
\r
15758 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
\r
15759 #define ETH_MMCRIR_RFAES_Pos (6U)
\r
15760 #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
\r
15761 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
\r
15762 #define ETH_MMCRIR_RFCES_Pos (5U)
\r
15763 #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
\r
15764 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
\r
15766 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
\r
15767 #define ETH_MMCTIR_TGFS_Pos (21U)
\r
15768 #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
\r
15769 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
\r
15770 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
\r
15771 #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
\r
15772 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
\r
15773 #define ETH_MMCTIR_TGFSCS_Pos (14U)
\r
15774 #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
\r
15775 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
\r
15777 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
\r
15778 #define ETH_MMCRIMR_RGUFM_Pos (17U)
\r
15779 #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
\r
15780 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
\r
15781 #define ETH_MMCRIMR_RFAEM_Pos (6U)
\r
15782 #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
\r
15783 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
\r
15784 #define ETH_MMCRIMR_RFCEM_Pos (5U)
\r
15785 #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
\r
15786 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
\r
15788 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
\r
15789 #define ETH_MMCTIMR_TGFM_Pos (21U)
\r
15790 #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
\r
15791 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
\r
15792 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
\r
15793 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
\r
15794 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
\r
15795 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
\r
15796 #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
\r
15797 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
\r
15799 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
\r
15800 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
\r
15801 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
\r
15802 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
\r
15804 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
\r
15805 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
\r
15806 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
\r
15807 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
\r
15809 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
\r
15810 #define ETH_MMCTGFCR_TGFC_Pos (0U)
\r
15811 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
\r
15812 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
\r
15814 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
\r
15815 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
\r
15816 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
\r
15817 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
\r
15819 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
\r
15820 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
\r
15821 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
\r
15822 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
\r
15824 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
\r
15825 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
\r
15826 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
\r
15827 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
\r
15829 /******************************************************************************/
\r
15830 /* Ethernet PTP Registers bits definition */
\r
15831 /******************************************************************************/
\r
15833 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
\r
15834 #define ETH_PTPTSCR_TSCNT_Pos (16U)
\r
15835 #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
\r
15836 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
\r
15837 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
\r
15838 #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
\r
15839 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
\r
15840 #define ETH_PTPTSSR_TSSEME_Pos (14U)
\r
15841 #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
\r
15842 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
\r
15843 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
\r
15844 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
\r
15845 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
\r
15846 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
\r
15847 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
\r
15848 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
\r
15849 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
\r
15850 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
\r
15851 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
\r
15852 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
\r
15853 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
\r
15854 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
\r
15855 #define ETH_PTPTSSR_TSSSR_Pos (9U)
\r
15856 #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
\r
15857 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
\r
15858 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
\r
15859 #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
\r
15860 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
\r
15862 #define ETH_PTPTSCR_TSARU_Pos (5U)
\r
15863 #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
\r
15864 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
\r
15865 #define ETH_PTPTSCR_TSITE_Pos (4U)
\r
15866 #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
\r
15867 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
\r
15868 #define ETH_PTPTSCR_TSSTU_Pos (3U)
\r
15869 #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
\r
15870 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
\r
15871 #define ETH_PTPTSCR_TSSTI_Pos (2U)
\r
15872 #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
\r
15873 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
\r
15874 #define ETH_PTPTSCR_TSFCU_Pos (1U)
\r
15875 #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
\r
15876 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
\r
15877 #define ETH_PTPTSCR_TSE_Pos (0U)
\r
15878 #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
\r
15879 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
\r
15881 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
\r
15882 #define ETH_PTPSSIR_STSSI_Pos (0U)
\r
15883 #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
\r
15884 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
\r
15886 /* Bit definition for Ethernet PTP Time Stamp High Register */
\r
15887 #define ETH_PTPTSHR_STS_Pos (0U)
\r
15888 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
\r
15889 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
\r
15891 /* Bit definition for Ethernet PTP Time Stamp Low Register */
\r
15892 #define ETH_PTPTSLR_STPNS_Pos (31U)
\r
15893 #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
\r
15894 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
\r
15895 #define ETH_PTPTSLR_STSS_Pos (0U)
\r
15896 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
\r
15897 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
\r
15899 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
\r
15900 #define ETH_PTPTSHUR_TSUS_Pos (0U)
\r
15901 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
\r
15902 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
\r
15904 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
\r
15905 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
\r
15906 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
\r
15907 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
\r
15908 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
\r
15909 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
\r
15910 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
\r
15912 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
\r
15913 #define ETH_PTPTSAR_TSA_Pos (0U)
\r
15914 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
\r
15915 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
\r
15917 /* Bit definition for Ethernet PTP Target Time High Register */
\r
15918 #define ETH_PTPTTHR_TTSH_Pos (0U)
\r
15919 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
\r
15920 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
\r
15922 /* Bit definition for Ethernet PTP Target Time Low Register */
\r
15923 #define ETH_PTPTTLR_TTSL_Pos (0U)
\r
15924 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
\r
15925 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
\r
15927 /* Bit definition for Ethernet PTP Time Stamp Status Register */
\r
15928 #define ETH_PTPTSSR_TSTTR_Pos (5U)
\r
15929 #define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
\r
15930 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
\r
15931 #define ETH_PTPTSSR_TSSO_Pos (4U)
\r
15932 #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
\r
15933 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
\r
15935 /******************************************************************************/
\r
15936 /* Ethernet DMA Registers bits definition */
\r
15937 /******************************************************************************/
\r
15939 /* Bit definition for Ethernet DMA Bus Mode Register */
\r
15940 #define ETH_DMABMR_AAB_Pos (25U)
\r
15941 #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
\r
15942 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
\r
15943 #define ETH_DMABMR_FPM_Pos (24U)
\r
15944 #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
\r
15945 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
\r
15946 #define ETH_DMABMR_USP_Pos (23U)
\r
15947 #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
\r
15948 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
\r
15949 #define ETH_DMABMR_RDP_Pos (17U)
\r
15950 #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
\r
15951 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
\r
15952 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
\r
15953 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
\r
15954 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
15955 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
15956 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
15957 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
15958 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
15959 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
15960 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
15961 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
15962 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
\r
15963 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
\r
15964 #define ETH_DMABMR_FB_Pos (16U)
\r
15965 #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
\r
15966 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
\r
15967 #define ETH_DMABMR_RTPR_Pos (14U)
\r
15968 #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
\r
15969 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
\r
15970 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
\r
15971 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
\r
15972 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
\r
15973 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
\r
15974 #define ETH_DMABMR_PBL_Pos (8U)
\r
15975 #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
\r
15976 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
\r
15977 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
\r
15978 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
\r
15979 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
15980 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
15981 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
15982 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
15983 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
15984 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
15985 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
15986 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
15987 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
\r
15988 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
\r
15989 #define ETH_DMABMR_EDE_Pos (7U)
\r
15990 #define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
\r
15991 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
\r
15992 #define ETH_DMABMR_DSL_Pos (2U)
\r
15993 #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
\r
15994 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
\r
15995 #define ETH_DMABMR_DA_Pos (1U)
\r
15996 #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
\r
15997 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
\r
15998 #define ETH_DMABMR_SR_Pos (0U)
\r
15999 #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
\r
16000 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
\r
16002 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
\r
16003 #define ETH_DMATPDR_TPD_Pos (0U)
\r
16004 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
\r
16005 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
\r
16007 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
\r
16008 #define ETH_DMARPDR_RPD_Pos (0U)
\r
16009 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
\r
16010 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
\r
16012 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
\r
16013 #define ETH_DMARDLAR_SRL_Pos (0U)
\r
16014 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
\r
16015 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
\r
16017 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
\r
16018 #define ETH_DMATDLAR_STL_Pos (0U)
\r
16019 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
\r
16020 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
\r
16022 /* Bit definition for Ethernet DMA Status Register */
\r
16023 #define ETH_DMASR_TSTS_Pos (29U)
\r
16024 #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
\r
16025 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
\r
16026 #define ETH_DMASR_PMTS_Pos (28U)
\r
16027 #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
\r
16028 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
\r
16029 #define ETH_DMASR_MMCS_Pos (27U)
\r
16030 #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
\r
16031 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
\r
16032 #define ETH_DMASR_EBS_Pos (23U)
\r
16033 #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
\r
16034 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
\r
16035 /* combination with EBS[2:0] for GetFlagStatus function */
\r
16036 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
\r
16037 #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
\r
16038 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
\r
16039 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
\r
16040 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
\r
16041 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
\r
16042 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
\r
16043 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
\r
16044 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
\r
16045 #define ETH_DMASR_TPS_Pos (20U)
\r
16046 #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
\r
16047 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
\r
16048 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
\r
16049 #define ETH_DMASR_TPS_Fetching_Pos (20U)
\r
16050 #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
\r
16051 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
\r
16052 #define ETH_DMASR_TPS_Waiting_Pos (21U)
\r
16053 #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
\r
16054 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
\r
16055 #define ETH_DMASR_TPS_Reading_Pos (20U)
\r
16056 #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
\r
16057 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
\r
16058 #define ETH_DMASR_TPS_Suspended_Pos (21U)
\r
16059 #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
\r
16060 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
\r
16061 #define ETH_DMASR_TPS_Closing_Pos (20U)
\r
16062 #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
\r
16063 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
\r
16064 #define ETH_DMASR_RPS_Pos (17U)
\r
16065 #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
\r
16066 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
\r
16067 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
\r
16068 #define ETH_DMASR_RPS_Fetching_Pos (17U)
\r
16069 #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
\r
16070 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
\r
16071 #define ETH_DMASR_RPS_Waiting_Pos (17U)
\r
16072 #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
\r
16073 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
\r
16074 #define ETH_DMASR_RPS_Suspended_Pos (19U)
\r
16075 #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
\r
16076 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
\r
16077 #define ETH_DMASR_RPS_Closing_Pos (17U)
\r
16078 #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
\r
16079 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
\r
16080 #define ETH_DMASR_RPS_Queuing_Pos (17U)
\r
16081 #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
\r
16082 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
\r
16083 #define ETH_DMASR_NIS_Pos (16U)
\r
16084 #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
\r
16085 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
\r
16086 #define ETH_DMASR_AIS_Pos (15U)
\r
16087 #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
\r
16088 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
\r
16089 #define ETH_DMASR_ERS_Pos (14U)
\r
16090 #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
\r
16091 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
\r
16092 #define ETH_DMASR_FBES_Pos (13U)
\r
16093 #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
\r
16094 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
\r
16095 #define ETH_DMASR_ETS_Pos (10U)
\r
16096 #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
\r
16097 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
\r
16098 #define ETH_DMASR_RWTS_Pos (9U)
\r
16099 #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
\r
16100 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
\r
16101 #define ETH_DMASR_RPSS_Pos (8U)
\r
16102 #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
\r
16103 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
\r
16104 #define ETH_DMASR_RBUS_Pos (7U)
\r
16105 #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
\r
16106 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
\r
16107 #define ETH_DMASR_RS_Pos (6U)
\r
16108 #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
\r
16109 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
\r
16110 #define ETH_DMASR_TUS_Pos (5U)
\r
16111 #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
\r
16112 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
\r
16113 #define ETH_DMASR_ROS_Pos (4U)
\r
16114 #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
\r
16115 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
\r
16116 #define ETH_DMASR_TJTS_Pos (3U)
\r
16117 #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
\r
16118 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
\r
16119 #define ETH_DMASR_TBUS_Pos (2U)
\r
16120 #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
\r
16121 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
\r
16122 #define ETH_DMASR_TPSS_Pos (1U)
\r
16123 #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
\r
16124 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
\r
16125 #define ETH_DMASR_TS_Pos (0U)
\r
16126 #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
\r
16127 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
\r
16129 /* Bit definition for Ethernet DMA Operation Mode Register */
\r
16130 #define ETH_DMAOMR_DTCEFD_Pos (26U)
\r
16131 #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
\r
16132 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
\r
16133 #define ETH_DMAOMR_RSF_Pos (25U)
\r
16134 #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
\r
16135 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
\r
16136 #define ETH_DMAOMR_DFRF_Pos (24U)
\r
16137 #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
\r
16138 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
\r
16139 #define ETH_DMAOMR_TSF_Pos (21U)
\r
16140 #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
\r
16141 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
\r
16142 #define ETH_DMAOMR_FTF_Pos (20U)
\r
16143 #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
\r
16144 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
\r
16145 #define ETH_DMAOMR_TTC_Pos (14U)
\r
16146 #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
\r
16147 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
\r
16148 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
\r
16149 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
\r
16150 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
\r
16151 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
\r
16152 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
\r
16153 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
\r
16154 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
\r
16155 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
\r
16156 #define ETH_DMAOMR_ST_Pos (13U)
\r
16157 #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
\r
16158 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
\r
16159 #define ETH_DMAOMR_FEF_Pos (7U)
\r
16160 #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
\r
16161 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
\r
16162 #define ETH_DMAOMR_FUGF_Pos (6U)
\r
16163 #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
\r
16164 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
\r
16165 #define ETH_DMAOMR_RTC_Pos (3U)
\r
16166 #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
\r
16167 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
\r
16168 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
\r
16169 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
\r
16170 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
\r
16171 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
\r
16172 #define ETH_DMAOMR_OSF_Pos (2U)
\r
16173 #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
\r
16174 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
\r
16175 #define ETH_DMAOMR_SR_Pos (1U)
\r
16176 #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
\r
16177 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
\r
16179 /* Bit definition for Ethernet DMA Interrupt Enable Register */
\r
16180 #define ETH_DMAIER_NISE_Pos (16U)
\r
16181 #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
\r
16182 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
\r
16183 #define ETH_DMAIER_AISE_Pos (15U)
\r
16184 #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
\r
16185 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
\r
16186 #define ETH_DMAIER_ERIE_Pos (14U)
\r
16187 #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
\r
16188 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
\r
16189 #define ETH_DMAIER_FBEIE_Pos (13U)
\r
16190 #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
\r
16191 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
\r
16192 #define ETH_DMAIER_ETIE_Pos (10U)
\r
16193 #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
\r
16194 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
\r
16195 #define ETH_DMAIER_RWTIE_Pos (9U)
\r
16196 #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
\r
16197 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
\r
16198 #define ETH_DMAIER_RPSIE_Pos (8U)
\r
16199 #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
\r
16200 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
\r
16201 #define ETH_DMAIER_RBUIE_Pos (7U)
\r
16202 #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
\r
16203 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
\r
16204 #define ETH_DMAIER_RIE_Pos (6U)
\r
16205 #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
\r
16206 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
\r
16207 #define ETH_DMAIER_TUIE_Pos (5U)
\r
16208 #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
\r
16209 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
\r
16210 #define ETH_DMAIER_ROIE_Pos (4U)
\r
16211 #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
\r
16212 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
\r
16213 #define ETH_DMAIER_TJTIE_Pos (3U)
\r
16214 #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
\r
16215 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
\r
16216 #define ETH_DMAIER_TBUIE_Pos (2U)
\r
16217 #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
\r
16218 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
\r
16219 #define ETH_DMAIER_TPSIE_Pos (1U)
\r
16220 #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
\r
16221 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
\r
16222 #define ETH_DMAIER_TIE_Pos (0U)
\r
16223 #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
\r
16224 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
\r
16226 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
\r
16227 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
\r
16228 #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
\r
16229 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
\r
16230 #define ETH_DMAMFBOCR_MFA_Pos (17U)
\r
16231 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
\r
16232 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
\r
16233 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
\r
16234 #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
\r
16235 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
\r
16236 #define ETH_DMAMFBOCR_MFC_Pos (0U)
\r
16237 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
\r
16238 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
\r
16240 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
\r
16241 #define ETH_DMACHTDR_HTDAP_Pos (0U)
\r
16242 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
\r
16243 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
\r
16245 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
\r
16246 #define ETH_DMACHRDR_HRDAP_Pos (0U)
\r
16247 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
\r
16248 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
\r
16250 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
\r
16251 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
\r
16252 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
\r
16253 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
\r
16255 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
\r
16256 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
\r
16257 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
\r
16258 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
\r
16260 /******************************************************************************/
\r
16264 /******************************************************************************/
\r
16265 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
\r
16266 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
\r
16267 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
\r
16268 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
\r
16269 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
\r
16270 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
\r
16271 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
\r
16272 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
\r
16273 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
\r
16274 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
\r
16275 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
\r
16276 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
\r
16277 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
\r
16278 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
\r
16279 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
\r
16280 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
\r
16281 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
\r
16282 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
\r
16283 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
\r
16284 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
\r
16285 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
\r
16286 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
\r
16287 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
\r
16288 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
\r
16289 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
\r
16290 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
\r
16291 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
\r
16292 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
\r
16293 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
\r
16294 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
\r
16295 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
\r
16296 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
\r
16297 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
\r
16298 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
\r
16299 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
\r
16300 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
\r
16301 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
\r
16302 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
\r
16303 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
\r
16304 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
\r
16305 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
\r
16306 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
\r
16307 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
\r
16308 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
\r
16309 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
\r
16310 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
\r
16311 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
\r
16312 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
\r
16313 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
\r
16314 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
\r
16315 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
\r
16316 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
\r
16317 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
\r
16318 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
\r
16319 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
\r
16321 /******************** Bit definition for USB_OTG_HCFG register ********************/
\r
16322 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
\r
16323 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
\r
16324 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
\r
16325 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
\r
16326 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
\r
16327 #define USB_OTG_HCFG_FSLSS_Pos (2U)
\r
16328 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
\r
16329 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
\r
16331 /******************** Bit definition for USB_OTG_DCFG register ********************/
\r
16332 #define USB_OTG_DCFG_DSPD_Pos (0U)
\r
16333 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
\r
16334 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
\r
16335 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
\r
16336 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
\r
16337 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
\r
16338 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
\r
16339 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
\r
16341 #define USB_OTG_DCFG_DAD_Pos (4U)
\r
16342 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
\r
16343 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
\r
16344 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
\r
16345 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
\r
16346 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
\r
16347 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
\r
16348 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
\r
16349 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
\r
16350 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
\r
16352 #define USB_OTG_DCFG_PFIVL_Pos (11U)
\r
16353 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
\r
16354 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
\r
16355 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
\r
16356 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
\r
16358 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
\r
16359 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
\r
16360 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
\r
16361 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
\r
16362 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
\r
16364 /******************** Bit definition for USB_OTG_PCGCR register ********************/
\r
16365 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
\r
16366 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
\r
16367 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
\r
16368 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
\r
16369 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
\r
16370 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
\r
16371 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
\r
16372 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
\r
16373 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
\r
16375 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
\r
16376 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
\r
16377 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
\r
16378 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
\r
16379 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
\r
16380 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
\r
16381 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
\r
16382 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
\r
16383 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
\r
16384 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
\r
16385 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
\r
16386 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
\r
16387 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
\r
16388 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
\r
16389 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
\r
16390 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
\r
16391 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
\r
16392 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
\r
16393 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
\r
16394 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
\r
16395 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
\r
16396 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
\r
16398 /******************** Bit definition for USB_OTG_DCTL register ********************/
\r
16399 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
\r
16400 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
\r
16401 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
\r
16402 #define USB_OTG_DCTL_SDIS_Pos (1U)
\r
16403 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
\r
16404 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
\r
16405 #define USB_OTG_DCTL_GINSTS_Pos (2U)
\r
16406 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
\r
16407 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
\r
16408 #define USB_OTG_DCTL_GONSTS_Pos (3U)
\r
16409 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
\r
16410 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
\r
16412 #define USB_OTG_DCTL_TCTL_Pos (4U)
\r
16413 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
\r
16414 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
\r
16415 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
\r
16416 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
\r
16417 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
\r
16418 #define USB_OTG_DCTL_SGINAK_Pos (7U)
\r
16419 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
\r
16420 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
\r
16421 #define USB_OTG_DCTL_CGINAK_Pos (8U)
\r
16422 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
\r
16423 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
\r
16424 #define USB_OTG_DCTL_SGONAK_Pos (9U)
\r
16425 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
\r
16426 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
\r
16427 #define USB_OTG_DCTL_CGONAK_Pos (10U)
\r
16428 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
\r
16429 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
\r
16430 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
\r
16431 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
\r
16432 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
\r
16434 /******************** Bit definition for USB_OTG_HFIR register ********************/
\r
16435 #define USB_OTG_HFIR_FRIVL_Pos (0U)
\r
16436 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
\r
16437 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
\r
16439 /******************** Bit definition for USB_OTG_HFNUM register ********************/
\r
16440 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
\r
16441 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
\r
16442 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
\r
16443 #define USB_OTG_HFNUM_FTREM_Pos (16U)
\r
16444 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
\r
16445 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
\r
16447 /******************** Bit definition for USB_OTG_DSTS register ********************/
\r
16448 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
\r
16449 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
\r
16450 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
\r
16452 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
\r
16453 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
\r
16454 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
\r
16455 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
\r
16456 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
\r
16457 #define USB_OTG_DSTS_EERR_Pos (3U)
\r
16458 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
\r
16459 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
\r
16460 #define USB_OTG_DSTS_FNSOF_Pos (8U)
\r
16461 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
\r
16462 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
\r
16464 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
\r
16465 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
\r
16466 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
\r
16467 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
\r
16468 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
\r
16469 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
\r
16470 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
\r
16471 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
\r
16472 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
\r
16473 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
\r
16474 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
\r
16475 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
\r
16476 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
\r
16477 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
\r
16478 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
\r
16479 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
\r
16480 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
\r
16481 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
\r
16482 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
\r
16483 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
\r
16484 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
\r
16486 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
\r
16487 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
\r
16488 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
\r
16489 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
\r
16490 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
\r
16491 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
\r
16492 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
\r
16493 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
\r
16494 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
\r
16495 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
\r
16496 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
\r
16497 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
\r
16498 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
\r
16499 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
\r
16500 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
\r
16501 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
\r
16502 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
\r
16503 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
\r
16504 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
\r
16505 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
\r
16506 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
\r
16507 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
\r
16508 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
\r
16509 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
\r
16510 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
\r
16511 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
\r
16512 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
\r
16513 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
\r
16514 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
\r
16515 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
\r
16516 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
\r
16517 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
\r
16518 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
\r
16519 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
\r
16520 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
\r
16521 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
\r
16522 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
\r
16523 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
\r
16524 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
\r
16525 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
\r
16526 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
\r
16527 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
\r
16528 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
\r
16529 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
\r
16530 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
\r
16531 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
\r
16532 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
\r
16533 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
\r
16534 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
\r
16535 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
\r
16536 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
\r
16537 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
\r
16538 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
\r
16539 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
\r
16540 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
\r
16541 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
\r
16542 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
\r
16543 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
\r
16544 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
\r
16545 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
\r
16546 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
\r
16547 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
\r
16549 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
\r
16550 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
\r
16551 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
\r
16552 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
\r
16553 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
\r
16554 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
\r
16555 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
\r
16556 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
\r
16557 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
\r
16558 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
\r
16559 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
\r
16560 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
\r
16561 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
\r
16562 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
\r
16563 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
\r
16564 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
\r
16565 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
\r
16566 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
\r
16567 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
\r
16568 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
\r
16569 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
\r
16570 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
\r
16571 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
\r
16572 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
\r
16573 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
\r
16574 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
\r
16575 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
\r
16576 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
\r
16577 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
\r
16578 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
\r
16580 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
\r
16581 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
\r
16582 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
\r
16583 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
16584 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
\r
16585 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
\r
16586 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
16587 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
\r
16588 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
\r
16589 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
\r
16590 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
\r
16591 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
\r
16592 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
\r
16593 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
\r
16594 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
\r
16595 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
\r
16596 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
\r
16597 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
\r
16598 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
\r
16599 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
\r
16600 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
\r
16601 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
\r
16602 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
\r
16603 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
\r
16604 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
\r
16606 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
\r
16607 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
\r
16608 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
\r
16609 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
\r
16610 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
\r
16611 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
\r
16612 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
\r
16613 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
\r
16614 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
\r
16615 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
\r
16616 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
\r
16617 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
\r
16618 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
\r
16619 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
\r
16620 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
\r
16622 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
\r
16623 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
\r
16624 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
\r
16625 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
\r
16626 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
\r
16627 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
\r
16628 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
\r
16629 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
\r
16630 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
\r
16631 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
\r
16632 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
\r
16634 /******************** Bit definition for USB_OTG_HAINT register ********************/
\r
16635 #define USB_OTG_HAINT_HAINT_Pos (0U)
\r
16636 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
\r
16637 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
\r
16639 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
\r
16640 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
\r
16641 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
\r
16642 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
16643 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
\r
16644 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
\r
16645 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
16646 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
\r
16647 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
\r
16648 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
\r
16649 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
\r
16650 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
\r
16651 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
\r
16652 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
\r
16653 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
\r
16654 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
\r
16655 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
\r
16656 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
\r
16657 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
\r
16658 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
\r
16659 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
\r
16660 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
\r
16661 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
\r
16662 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
\r
16663 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
\r
16664 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
\r
16665 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
\r
16666 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
\r
16667 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
\r
16668 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
\r
16669 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
\r
16670 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
\r
16671 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
\r
16672 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
\r
16673 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
\r
16674 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
\r
16675 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
\r
16677 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
\r
16678 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
\r
16679 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
\r
16680 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
\r
16681 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
\r
16682 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
\r
16683 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
\r
16684 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
\r
16685 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
\r
16686 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
\r
16687 #define USB_OTG_GINTSTS_SOF_Pos (3U)
\r
16688 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
\r
16689 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
\r
16690 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
\r
16691 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
\r
16692 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
\r
16693 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
\r
16694 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
\r
16695 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
\r
16696 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
\r
16697 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
\r
16698 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
\r
16699 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
\r
16700 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
\r
16701 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
\r
16702 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
\r
16703 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
\r
16704 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
\r
16705 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
\r
16706 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
\r
16707 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
\r
16708 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
\r
16709 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
\r
16710 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
\r
16711 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
\r
16712 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
\r
16713 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
\r
16714 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
\r
16715 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
\r
16716 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
\r
16717 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
\r
16718 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
\r
16719 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
\r
16720 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
\r
16721 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
\r
16722 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
\r
16723 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
\r
16724 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
\r
16725 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
\r
16726 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
\r
16727 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
\r
16728 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
\r
16729 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
\r
16730 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
\r
16731 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
\r
16732 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
\r
16733 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
\r
16734 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
\r
16735 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
\r
16736 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
\r
16737 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
\r
16738 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
\r
16739 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
\r
16740 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
\r
16741 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
\r
16742 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
\r
16743 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
\r
16744 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
\r
16745 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
\r
16746 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
\r
16747 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
\r
16748 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
\r
16749 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
\r
16750 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
\r
16751 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
\r
16752 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
\r
16753 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
\r
16754 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
\r
16755 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
\r
16756 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
\r
16757 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
\r
16758 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
\r
16759 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
\r
16760 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
\r
16761 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
\r
16763 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
\r
16764 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
\r
16765 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
\r
16766 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
\r
16767 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
\r
16768 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
\r
16769 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
\r
16770 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
\r
16771 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
\r
16772 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
\r
16773 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
\r
16774 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
\r
16775 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
\r
16776 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
\r
16777 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
\r
16778 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
\r
16779 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
\r
16780 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
\r
16781 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
\r
16782 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
\r
16783 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
\r
16784 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
\r
16785 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
\r
16786 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
\r
16787 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
\r
16788 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
\r
16789 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
\r
16790 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
\r
16791 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
\r
16792 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
\r
16793 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
\r
16794 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
\r
16795 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
\r
16796 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
\r
16797 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
\r
16798 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
\r
16799 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
\r
16800 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
\r
16801 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
\r
16802 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
\r
16803 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
\r
16804 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
\r
16805 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
\r
16806 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
\r
16807 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
\r
16808 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
\r
16809 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
\r
16810 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
\r
16811 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
\r
16812 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
\r
16813 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
\r
16814 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
\r
16815 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
\r
16816 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
\r
16817 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
\r
16818 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
\r
16819 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
\r
16820 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
\r
16821 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
\r
16822 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
\r
16823 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
\r
16824 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
\r
16825 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
\r
16826 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
\r
16827 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
\r
16828 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
\r
16829 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
\r
16830 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
\r
16831 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
\r
16832 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
\r
16833 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
\r
16834 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
\r
16835 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
\r
16836 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
\r
16837 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
\r
16838 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
\r
16839 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
\r
16840 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
\r
16841 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
\r
16842 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
\r
16843 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
\r
16844 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
\r
16845 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
\r
16846 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
\r
16847 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
\r
16849 /******************** Bit definition for USB_OTG_DAINT register ********************/
\r
16850 #define USB_OTG_DAINT_IEPINT_Pos (0U)
\r
16851 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
\r
16852 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
\r
16853 #define USB_OTG_DAINT_OEPINT_Pos (16U)
\r
16854 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
\r
16855 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
\r
16857 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
\r
16858 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
\r
16859 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
\r
16860 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
\r
16862 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
\r
16863 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
\r
16864 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
\r
16865 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
\r
16866 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
\r
16867 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
\r
16868 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
\r
16869 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
\r
16870 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
\r
16871 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
\r
16872 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
\r
16873 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
\r
16874 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
\r
16876 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
\r
16877 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
\r
16878 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
\r
16879 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
\r
16880 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
\r
16881 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
\r
16882 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
\r
16884 /******************** Bit definition for OTG register ********************/
\r
16886 #define USB_OTG_CHNUM_Pos (0U)
\r
16887 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
\r
16888 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
\r
16889 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
\r
16890 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
\r
16891 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
\r
16892 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
\r
16893 #define USB_OTG_BCNT_Pos (4U)
\r
16894 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
\r
16895 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
\r
16897 #define USB_OTG_DPID_Pos (15U)
\r
16898 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
\r
16899 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
\r
16900 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
\r
16901 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
\r
16903 #define USB_OTG_PKTSTS_Pos (17U)
\r
16904 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
\r
16905 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
\r
16906 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
\r
16907 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
\r
16908 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
\r
16909 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
\r
16911 #define USB_OTG_EPNUM_Pos (0U)
\r
16912 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
\r
16913 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
\r
16914 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
\r
16915 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
\r
16916 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
\r
16917 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
\r
16919 #define USB_OTG_FRMNUM_Pos (21U)
\r
16920 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
\r
16921 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
\r
16922 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
\r
16923 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
\r
16924 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
\r
16925 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
\r
16927 /******************** Bit definition for OTG register ********************/
\r
16929 #define USB_OTG_CHNUM_Pos (0U)
\r
16930 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
\r
16931 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
\r
16932 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
\r
16933 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
\r
16934 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
\r
16935 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
\r
16936 #define USB_OTG_BCNT_Pos (4U)
\r
16937 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
\r
16938 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
\r
16940 #define USB_OTG_DPID_Pos (15U)
\r
16941 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
\r
16942 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
\r
16943 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
\r
16944 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
\r
16946 #define USB_OTG_PKTSTS_Pos (17U)
\r
16947 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
\r
16948 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
\r
16949 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
\r
16950 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
\r
16951 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
\r
16952 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
\r
16954 #define USB_OTG_EPNUM_Pos (0U)
\r
16955 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
\r
16956 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
\r
16957 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
\r
16958 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
\r
16959 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
\r
16960 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
\r
16962 #define USB_OTG_FRMNUM_Pos (21U)
\r
16963 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
\r
16964 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
\r
16965 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
\r
16966 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
\r
16967 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
\r
16968 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
\r
16970 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
\r
16971 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
\r
16972 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
\r
16973 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
\r
16975 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
\r
16976 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
\r
16977 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
\r
16978 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
\r
16980 /******************** Bit definition for OTG register ********************/
\r
16981 #define USB_OTG_NPTXFSA_Pos (0U)
\r
16982 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
\r
16983 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
\r
16984 #define USB_OTG_NPTXFD_Pos (16U)
\r
16985 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
\r
16986 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
\r
16987 #define USB_OTG_TX0FSA_Pos (0U)
\r
16988 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
\r
16989 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
\r
16990 #define USB_OTG_TX0FD_Pos (16U)
\r
16991 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
\r
16992 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
\r
16994 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
\r
16995 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
\r
16996 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
\r
16997 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
\r
16999 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
\r
17000 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
\r
17001 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
\r
17002 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
\r
17004 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
\r
17005 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
\r
17006 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
\r
17007 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
\r
17008 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
\r
17009 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
\r
17010 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
\r
17011 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
\r
17012 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
\r
17013 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
\r
17014 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
\r
17016 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
\r
17017 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
\r
17018 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
\r
17019 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
\r
17020 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
\r
17021 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
\r
17022 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
\r
17023 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
\r
17024 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
\r
17025 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
\r
17027 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
\r
17028 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
\r
17029 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
\r
17030 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
\r
17031 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
\r
17032 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
\r
17033 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
\r
17035 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
\r
17036 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
\r
17037 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
\r
17038 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
\r
17039 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
\r
17040 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
\r
17041 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
\r
17042 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
\r
17043 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
\r
17044 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
\r
17045 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
\r
17046 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
\r
17047 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
\r
17048 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
\r
17049 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
\r
17051 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
\r
17052 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
\r
17053 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
\r
17054 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
\r
17055 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
\r
17056 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
\r
17057 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
\r
17058 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
\r
17059 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
\r
17060 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
\r
17061 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
\r
17062 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
\r
17063 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
\r
17064 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
\r
17065 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
\r
17067 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
\r
17068 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
\r
17069 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
\r
17070 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
\r
17072 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
\r
17073 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
\r
17074 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
\r
17075 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
\r
17076 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
\r
17077 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
\r
17078 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
\r
17080 /******************** Bit definition for USB_OTG_GCCFG register ********************/
\r
17081 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
\r
17082 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
\r
17083 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
\r
17084 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
\r
17085 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
\r
17086 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
\r
17088 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
\r
17089 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
\r
17090 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
\r
17091 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
\r
17092 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
\r
17093 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
\r
17094 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
\r
17096 /******************** Bit definition for USB_OTG_CID register ********************/
\r
17097 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
\r
17098 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
\r
17099 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
\r
17101 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
\r
17102 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
\r
17103 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
\r
17104 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
\r
17105 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
\r
17106 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
\r
17107 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
\r
17108 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
\r
17109 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
\r
17110 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
\r
17111 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
\r
17112 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
\r
17113 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
\r
17114 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
\r
17115 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
\r
17116 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
\r
17117 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
\r
17118 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
\r
17119 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
\r
17120 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
\r
17121 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
\r
17122 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
\r
17123 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
\r
17124 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
\r
17125 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
\r
17126 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
\r
17127 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
\r
17128 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
\r
17129 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
\r
17130 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
\r
17131 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
\r
17132 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
\r
17133 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
\r
17134 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
\r
17135 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
\r
17136 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
\r
17137 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
\r
17138 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
\r
17139 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
\r
17140 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
\r
17141 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
\r
17142 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
\r
17143 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
\r
17144 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
\r
17145 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
\r
17146 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
\r
17148 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
\r
17149 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
\r
17150 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
\r
17151 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
17152 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
\r
17153 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
\r
17154 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
17155 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
\r
17156 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
\r
17157 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
\r
17158 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
\r
17159 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
\r
17160 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
\r
17161 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
\r
17162 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
\r
17163 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
\r
17164 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
\r
17165 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
\r
17166 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
\r
17167 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
\r
17168 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
\r
17169 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
\r
17170 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
\r
17171 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
\r
17172 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
\r
17173 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
\r
17174 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
\r
17175 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
\r
17177 /******************** Bit definition for USB_OTG_HPRT register ********************/
\r
17178 #define USB_OTG_HPRT_PCSTS_Pos (0U)
\r
17179 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
\r
17180 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
\r
17181 #define USB_OTG_HPRT_PCDET_Pos (1U)
\r
17182 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
\r
17183 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
\r
17184 #define USB_OTG_HPRT_PENA_Pos (2U)
\r
17185 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
\r
17186 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
\r
17187 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
\r
17188 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
\r
17189 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
\r
17190 #define USB_OTG_HPRT_POCA_Pos (4U)
\r
17191 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
\r
17192 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
\r
17193 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
\r
17194 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
\r
17195 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
\r
17196 #define USB_OTG_HPRT_PRES_Pos (6U)
\r
17197 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
\r
17198 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
\r
17199 #define USB_OTG_HPRT_PSUSP_Pos (7U)
\r
17200 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
\r
17201 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
\r
17202 #define USB_OTG_HPRT_PRST_Pos (8U)
\r
17203 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
\r
17204 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
\r
17206 #define USB_OTG_HPRT_PLSTS_Pos (10U)
\r
17207 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
\r
17208 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
\r
17209 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
\r
17210 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
\r
17211 #define USB_OTG_HPRT_PPWR_Pos (12U)
\r
17212 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
\r
17213 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
\r
17215 #define USB_OTG_HPRT_PTCTL_Pos (13U)
\r
17216 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
\r
17217 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
\r
17218 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
\r
17219 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
\r
17220 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
\r
17221 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
\r
17223 #define USB_OTG_HPRT_PSPD_Pos (17U)
\r
17224 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
\r
17225 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
\r
17226 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
\r
17227 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
\r
17229 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
\r
17230 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
\r
17231 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
\r
17232 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
17233 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
\r
17234 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
\r
17235 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
17236 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
\r
17237 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
\r
17238 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
\r
17239 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
\r
17240 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
\r
17241 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
\r
17242 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
\r
17243 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
\r
17244 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
\r
17245 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
\r
17246 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
\r
17247 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
\r
17248 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
\r
17249 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
\r
17250 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
\r
17251 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
\r
17252 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
\r
17253 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
\r
17254 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
\r
17255 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
\r
17256 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
\r
17257 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
\r
17258 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
\r
17259 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
\r
17260 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
\r
17261 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
\r
17262 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
\r
17264 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
\r
17265 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
\r
17266 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
\r
17267 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
\r
17268 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
\r
17269 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
\r
17270 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
\r
17272 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
\r
17273 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
\r
17274 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
\r
17275 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
\r
17276 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
\r
17277 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
\r
17278 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
\r
17279 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
\r
17280 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
\r
17281 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
\r
17282 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
\r
17283 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
\r
17284 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
\r
17286 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
\r
17287 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
\r
17288 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
\r
17289 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
\r
17290 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
\r
17291 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
\r
17292 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
\r
17293 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
\r
17295 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
\r
17296 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
\r
17297 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
\r
17298 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
\r
17299 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
\r
17300 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
\r
17301 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
\r
17302 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
\r
17303 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
\r
17304 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
\r
17305 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
\r
17306 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
\r
17307 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
\r
17308 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
\r
17309 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
\r
17310 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
\r
17311 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
\r
17312 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
\r
17313 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
\r
17314 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
\r
17315 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
\r
17316 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
\r
17317 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
\r
17318 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
\r
17319 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
\r
17321 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
\r
17322 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
\r
17323 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
\r
17324 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
\r
17326 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
\r
17327 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
\r
17328 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
\r
17329 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
\r
17330 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
\r
17331 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
\r
17332 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
\r
17333 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
\r
17334 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
\r
17335 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
\r
17336 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
\r
17337 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
\r
17338 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
\r
17340 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
\r
17341 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
\r
17342 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
\r
17343 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
\r
17344 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
\r
17346 #define USB_OTG_HCCHAR_MC_Pos (20U)
\r
17347 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
\r
17348 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
\r
17349 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
\r
17350 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
\r
17352 #define USB_OTG_HCCHAR_DAD_Pos (22U)
\r
17353 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
\r
17354 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
\r
17355 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
\r
17356 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
\r
17357 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
\r
17358 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
\r
17359 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
\r
17360 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
\r
17361 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
\r
17362 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
\r
17363 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
\r
17364 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
\r
17365 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
\r
17366 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
\r
17367 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
\r
17368 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
\r
17369 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
\r
17370 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
\r
17372 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
\r
17374 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
\r
17375 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
\r
17376 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
\r
17377 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
\r
17378 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
\r
17379 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
\r
17380 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
\r
17381 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
\r
17382 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
\r
17383 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
\r
17385 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
\r
17386 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
\r
17387 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
\r
17388 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
\r
17389 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
\r
17390 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
\r
17391 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
\r
17392 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
\r
17393 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
\r
17394 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
\r
17396 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
\r
17397 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
\r
17398 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
\r
17399 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
\r
17400 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
\r
17401 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
\r
17402 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
\r
17403 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
\r
17404 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
\r
17405 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
\r
17406 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
\r
17408 /******************** Bit definition for USB_OTG_HCINT register ********************/
\r
17409 #define USB_OTG_HCINT_XFRC_Pos (0U)
\r
17410 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
\r
17411 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
\r
17412 #define USB_OTG_HCINT_CHH_Pos (1U)
\r
17413 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
\r
17414 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
\r
17415 #define USB_OTG_HCINT_AHBERR_Pos (2U)
\r
17416 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
\r
17417 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
\r
17418 #define USB_OTG_HCINT_STALL_Pos (3U)
\r
17419 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
\r
17420 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
\r
17421 #define USB_OTG_HCINT_NAK_Pos (4U)
\r
17422 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
\r
17423 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
\r
17424 #define USB_OTG_HCINT_ACK_Pos (5U)
\r
17425 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
\r
17426 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
\r
17427 #define USB_OTG_HCINT_NYET_Pos (6U)
\r
17428 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
\r
17429 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
\r
17430 #define USB_OTG_HCINT_TXERR_Pos (7U)
\r
17431 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
\r
17432 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
\r
17433 #define USB_OTG_HCINT_BBERR_Pos (8U)
\r
17434 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
\r
17435 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
\r
17436 #define USB_OTG_HCINT_FRMOR_Pos (9U)
\r
17437 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
\r
17438 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
\r
17439 #define USB_OTG_HCINT_DTERR_Pos (10U)
\r
17440 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
\r
17441 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
\r
17443 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
\r
17444 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
\r
17445 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
\r
17446 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
\r
17447 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
\r
17448 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
\r
17449 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
\r
17450 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
\r
17451 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
\r
17452 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
\r
17453 #define USB_OTG_DIEPINT_TOC_Pos (3U)
\r
17454 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
\r
17455 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
\r
17456 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
\r
17457 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
\r
17458 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
\r
17459 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
\r
17460 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
\r
17461 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
\r
17462 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
\r
17463 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
\r
17464 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
\r
17465 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
\r
17466 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
\r
17467 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
\r
17468 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
\r
17469 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
\r
17470 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
\r
17471 #define USB_OTG_DIEPINT_BNA_Pos (9U)
\r
17472 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
\r
17473 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
\r
17474 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
\r
17475 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
\r
17476 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
\r
17477 #define USB_OTG_DIEPINT_BERR_Pos (12U)
\r
17478 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
\r
17479 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
\r
17480 #define USB_OTG_DIEPINT_NAK_Pos (13U)
\r
17481 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
\r
17482 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
\r
17484 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
\r
17485 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
\r
17486 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
\r
17487 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
\r
17488 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
\r
17489 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
\r
17490 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
\r
17491 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
\r
17492 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
\r
17493 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
\r
17494 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
\r
17495 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
\r
17496 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
\r
17497 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
\r
17498 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
\r
17499 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
\r
17500 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
\r
17501 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
\r
17502 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
\r
17503 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
\r
17504 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
\r
17505 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
\r
17506 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
\r
17507 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
\r
17508 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
\r
17509 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
\r
17510 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
\r
17511 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
\r
17512 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
\r
17513 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
\r
17514 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
\r
17515 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
\r
17516 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
\r
17517 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
\r
17519 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
\r
17521 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
\r
17522 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
\r
17523 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
\r
17524 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
\r
17525 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
\r
17526 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
\r
17527 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
\r
17528 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
\r
17529 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
\r
17530 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
\r
17531 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
\r
17532 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
\r
17533 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
\r
17534 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
\r
17535 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
\r
17536 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
\r
17537 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
\r
17538 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
\r
17539 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
\r
17540 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
\r
17541 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
\r
17542 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
\r
17543 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
\r
17544 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
\r
17546 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
\r
17547 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
\r
17548 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
\r
17549 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
\r
17551 /******************** Bit definition for USB_OTG_HCDMA register ********************/
\r
17552 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
\r
17553 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
\r
17554 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
\r
17556 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
\r
17557 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
\r
17558 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
\r
17559 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
\r
17561 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
\r
17562 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
\r
17563 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
\r
17564 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
\r
17565 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
\r
17566 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
\r
17567 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
\r
17569 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
\r
17570 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
\r
17571 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
\r
17572 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
\r
17573 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
\r
17574 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
\r
17575 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
\r
17576 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
\r
17577 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
\r
17578 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
\r
17579 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
\r
17580 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
\r
17581 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
\r
17582 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
\r
17583 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
\r
17584 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
\r
17585 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
\r
17586 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
\r
17587 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
\r
17588 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
\r
17589 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
\r
17590 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
\r
17591 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
\r
17592 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
\r
17593 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
\r
17594 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
\r
17595 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
\r
17596 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
\r
17597 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
\r
17598 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
\r
17599 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
\r
17600 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
\r
17601 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
\r
17602 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
\r
17603 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
\r
17604 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
\r
17605 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
\r
17606 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
\r
17607 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
\r
17609 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
\r
17610 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
\r
17611 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
\r
17612 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
\r
17613 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
\r
17614 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
\r
17615 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
\r
17616 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
\r
17617 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
\r
17618 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
\r
17619 #define USB_OTG_DOEPINT_STUP_Pos (3U)
\r
17620 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
\r
17621 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
\r
17622 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
\r
17623 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
\r
17624 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
\r
17625 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
\r
17626 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
\r
17627 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
\r
17628 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
\r
17629 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
\r
17630 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
\r
17631 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
\r
17632 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
\r
17633 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
\r
17634 #define USB_OTG_DOEPINT_NAK_Pos (13U)
\r
17635 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
\r
17636 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
\r
17637 #define USB_OTG_DOEPINT_NYET_Pos (14U)
\r
17638 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
\r
17639 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
\r
17640 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
\r
17641 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
\r
17642 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
\r
17644 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
\r
17645 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
\r
17646 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
\r
17647 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
\r
17648 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
\r
17649 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
\r
17650 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
\r
17652 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
\r
17653 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
\r
17654 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
\r
17655 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
\r
17656 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
\r
17658 /******************** Bit definition for PCGCCTL register ********************/
\r
17659 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
\r
17660 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
\r
17661 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
\r
17662 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
\r
17663 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
\r
17664 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
\r
17665 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
\r
17666 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
\r
17667 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
\r
17670 /******************************************************************************/
\r
17672 /* JPEG Encoder/Decoder */
\r
17674 /******************************************************************************/
\r
17675 /******************** Bit definition for CONFR0 register ********************/
\r
17676 #define JPEG_CONFR0_START_Pos (0U)
\r
17677 #define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
\r
17678 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
\r
17680 /******************** Bit definition for CONFR1 register *******************/
\r
17681 #define JPEG_CONFR1_NF_Pos (0U)
\r
17682 #define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
\r
17683 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
\r
17684 #define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
\r
17685 #define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
\r
17686 #define JPEG_CONFR1_RE_Pos (2U)
\r
17687 #define JPEG_CONFR1_RE_Msk (0x1UL << JPEG_CONFR1_RE_Pos) /*!< 0x00000004 */
\r
17688 #define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk /*!<Restart maker Enable */
\r
17689 #define JPEG_CONFR1_DE_Pos (3U)
\r
17690 #define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
\r
17691 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
\r
17692 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
\r
17693 #define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
\r
17694 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
\r
17695 #define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
\r
17696 #define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
\r
17697 #define JPEG_CONFR1_NS_Pos (6U)
\r
17698 #define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
\r
17699 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
\r
17700 #define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
\r
17701 #define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
\r
17702 #define JPEG_CONFR1_HDR_Pos (8U)
\r
17703 #define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
\r
17704 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
\r
17705 #define JPEG_CONFR1_YSIZE_Pos (16U)
\r
17706 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
\r
17707 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
\r
17709 /******************** Bit definition for CONFR2 register *******************/
\r
17710 #define JPEG_CONFR2_NMCU_Pos (0U)
\r
17711 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
\r
17712 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
\r
17714 /******************** Bit definition for CONFR3 register *******************/
\r
17715 #define JPEG_CONFR3_NRST_Pos (0U)
\r
17716 #define JPEG_CONFR3_NRST_Msk (0xFFFFUL << JPEG_CONFR3_NRST_Pos) /*!< 0x0000FFFF */
\r
17717 #define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk /*!<Number of MCU between two restart makers minus 1 */
\r
17718 #define JPEG_CONFR3_XSIZE_Pos (16U)
\r
17719 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
\r
17720 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
\r
17722 /******************** Bit definition for CONFR4 register *******************/
\r
17723 #define JPEG_CONFR4_HD_Pos (0U)
\r
17724 #define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
\r
17725 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
17726 #define JPEG_CONFR4_HA_Pos (1U)
\r
17727 #define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
\r
17728 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
17729 #define JPEG_CONFR4_QT_Pos (2U)
\r
17730 #define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
\r
17731 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
\r
17732 #define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
\r
17733 #define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
\r
17734 #define JPEG_CONFR4_NB_Pos (4U)
\r
17735 #define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
\r
17736 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
17737 #define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
\r
17738 #define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
\r
17739 #define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
\r
17740 #define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
\r
17741 #define JPEG_CONFR4_VSF_Pos (8U)
\r
17742 #define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
\r
17743 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
\r
17744 #define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
\r
17745 #define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
\r
17746 #define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
\r
17747 #define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
\r
17748 #define JPEG_CONFR4_HSF_Pos (12U)
\r
17749 #define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
\r
17750 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
\r
17751 #define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
\r
17752 #define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
\r
17753 #define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
\r
17754 #define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
\r
17756 /******************** Bit definition for CONFR5 register *******************/
\r
17757 #define JPEG_CONFR5_HD_Pos (0U)
\r
17758 #define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
\r
17759 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
17760 #define JPEG_CONFR5_HA_Pos (1U)
\r
17761 #define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
\r
17762 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
17763 #define JPEG_CONFR5_QT_Pos (2U)
\r
17764 #define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
\r
17765 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
\r
17766 #define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
\r
17767 #define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
\r
17768 #define JPEG_CONFR5_NB_Pos (4U)
\r
17769 #define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
\r
17770 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
17771 #define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
\r
17772 #define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
\r
17773 #define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
\r
17774 #define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
\r
17775 #define JPEG_CONFR5_VSF_Pos (8U)
\r
17776 #define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
\r
17777 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
\r
17778 #define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
\r
17779 #define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
\r
17780 #define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
\r
17781 #define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
\r
17782 #define JPEG_CONFR5_HSF_Pos (12U)
\r
17783 #define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
\r
17784 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
\r
17785 #define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
\r
17786 #define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
\r
17787 #define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
\r
17788 #define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
\r
17790 /******************** Bit definition for CONFR6 register *******************/
\r
17791 #define JPEG_CONFR6_HD_Pos (0U)
\r
17792 #define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
\r
17793 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
17794 #define JPEG_CONFR6_HA_Pos (1U)
\r
17795 #define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
\r
17796 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
17797 #define JPEG_CONFR6_QT_Pos (2U)
\r
17798 #define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
\r
17799 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
\r
17800 #define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
\r
17801 #define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
\r
17802 #define JPEG_CONFR6_NB_Pos (4U)
\r
17803 #define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
\r
17804 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
17805 #define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
\r
17806 #define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
\r
17807 #define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
\r
17808 #define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
\r
17809 #define JPEG_CONFR6_VSF_Pos (8U)
\r
17810 #define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
\r
17811 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
\r
17812 #define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
\r
17813 #define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
\r
17814 #define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
\r
17815 #define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
\r
17816 #define JPEG_CONFR6_HSF_Pos (12U)
\r
17817 #define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
\r
17818 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
\r
17819 #define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
\r
17820 #define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
\r
17821 #define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
\r
17822 #define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
\r
17824 /******************** Bit definition for CONFR7 register *******************/
\r
17825 #define JPEG_CONFR7_HD_Pos (0U)
\r
17826 #define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
\r
17827 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
17828 #define JPEG_CONFR7_HA_Pos (1U)
\r
17829 #define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
\r
17830 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
17831 #define JPEG_CONFR7_QT_Pos (2U)
\r
17832 #define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
\r
17833 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
\r
17834 #define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
\r
17835 #define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
\r
17836 #define JPEG_CONFR7_NB_Pos (4U)
\r
17837 #define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
\r
17838 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
17839 #define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
\r
17840 #define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
\r
17841 #define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
\r
17842 #define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
\r
17843 #define JPEG_CONFR7_VSF_Pos (8U)
\r
17844 #define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
\r
17845 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
\r
17846 #define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
\r
17847 #define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
\r
17848 #define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
\r
17849 #define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
\r
17850 #define JPEG_CONFR7_HSF_Pos (12U)
\r
17851 #define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
\r
17852 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
\r
17853 #define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
\r
17854 #define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
\r
17855 #define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
\r
17856 #define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
\r
17858 /******************** Bit definition for CR register *******************/
\r
17859 #define JPEG_CR_JCEN_Pos (0U)
\r
17860 #define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
\r
17861 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
\r
17862 #define JPEG_CR_IFTIE_Pos (1U)
\r
17863 #define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
\r
17864 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
\r
17865 #define JPEG_CR_IFNFIE_Pos (2U)
\r
17866 #define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
\r
17867 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
\r
17868 #define JPEG_CR_OFTIE_Pos (3U)
\r
17869 #define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
\r
17870 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
\r
17871 #define JPEG_CR_OFNEIE_Pos (4U)
\r
17872 #define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
\r
17873 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
\r
17874 #define JPEG_CR_EOCIE_Pos (5U)
\r
17875 #define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
\r
17876 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
\r
17877 #define JPEG_CR_HPDIE_Pos (6U)
\r
17878 #define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
\r
17879 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
\r
17880 #define JPEG_CR_IDMAEN_Pos (11U)
\r
17881 #define JPEG_CR_IDMAEN_Msk (0x1UL << JPEG_CR_IDMAEN_Pos) /*!< 0x00000800 */
\r
17882 #define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk /*!<Enable the DMA request generation for the input FIFO */
\r
17883 #define JPEG_CR_ODMAEN_Pos (12U)
\r
17884 #define JPEG_CR_ODMAEN_Msk (0x1UL << JPEG_CR_ODMAEN_Pos) /*!< 0x00001000 */
\r
17885 #define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk /*!<Enable the DMA request generation for the output FIFO */
\r
17886 #define JPEG_CR_IFF_Pos (13U)
\r
17887 #define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
\r
17888 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
\r
17889 #define JPEG_CR_OFF_Pos (14U)
\r
17890 #define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
\r
17891 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
\r
17893 /******************** Bit definition for SR register *******************/
\r
17894 #define JPEG_SR_IFTF_Pos (1U)
\r
17895 #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
\r
17896 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
\r
17897 #define JPEG_SR_IFNFF_Pos (2U)
\r
17898 #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
\r
17899 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
\r
17900 #define JPEG_SR_OFTF_Pos (3U)
\r
17901 #define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
\r
17902 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
\r
17903 #define JPEG_SR_OFNEF_Pos (4U)
\r
17904 #define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000001 */
\r
17905 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
\r
17906 #define JPEG_SR_EOCF_Pos (5U)
\r
17907 #define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000002 */
\r
17908 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
\r
17909 #define JPEG_SR_HPDF_Pos (6U)
\r
17910 #define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000004 */
\r
17911 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
\r
17912 #define JPEG_SR_COF_Pos (7U)
\r
17913 #define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000008 */
\r
17914 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
\r
17916 /******************** Bit definition for CFR register *******************/
\r
17917 #define JPEG_CFR_CEOCF_Pos (5U)
\r
17918 #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000020 */
\r
17919 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
\r
17920 #define JPEG_CFR_CHPDF_Pos (6U)
\r
17921 #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000040 */
\r
17922 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
\r
17924 /******************** Bit definition for DIR register ********************/
\r
17925 #define JPEG_DIR_DATAIN_Pos (0U)
\r
17926 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
\r
17927 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
\r
17929 /******************** Bit definition for DOR register ********************/
\r
17930 #define JPEG_DOR_DATAOUT_Pos (0U)
\r
17931 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
\r
17932 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
\r
17934 /******************************************************************************/
\r
17938 /******************************************************************************/
\r
17939 /******************** Bit definition for MDIOS_CR register *******************/
\r
17940 #define MDIOS_CR_EN_Pos (0U)
\r
17941 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
\r
17942 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!<Peripheral enable */
\r
17943 #define MDIOS_CR_WRIE_Pos (1U)
\r
17944 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
\r
17945 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!<Register write interrupt enable */
\r
17946 #define MDIOS_CR_RDIE_Pos (2U)
\r
17947 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
\r
17948 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!<Register Read Interrupt Enable */
\r
17949 #define MDIOS_CR_EIE_Pos (3U)
\r
17950 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
\r
17951 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!<Error interrupt enable */
\r
17952 #define MDIOS_CR_DPC_Pos (7U)
\r
17953 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
\r
17954 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!<Disable Preamble Check */
\r
17955 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
\r
17956 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
\r
17957 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!<PORT_ADDRESS[4:0] bits */
\r
17958 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
\r
17959 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
\r
17960 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
\r
17961 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
\r
17962 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
\r
17964 /******************** Bit definition for MDIOS_WRFR register *******************/
\r
17965 #define MDIOS_WRFR_WRF_Pos (0U)
\r
17966 #define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFUL << MDIOS_WRFR_WRF_Pos) /*!< 0xFFFFFFFF */
\r
17967 #define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
\r
17969 /******************** Bit definition for MDIOS_CWRFR register *******************/
\r
17970 #define MDIOS_CWRFR_CWRF_Pos (0U)
\r
17971 #define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFUL << MDIOS_CWRFR_CWRF_Pos) /*!< 0xFFFFFFFF */
\r
17972 #define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
\r
17974 /******************** Bit definition for MDIOS_RDFR register *******************/
\r
17975 #define MDIOS_RDFR_RDF_Pos (0U)
\r
17976 #define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFUL << MDIOS_RDFR_RDF_Pos) /*!< 0xFFFFFFFF */
\r
17977 #define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
\r
17979 /******************** Bit definition for MDIOS_CRDFR register *******************/
\r
17980 #define MDIOS_CRDFR_CRDF_Pos (0U)
\r
17981 #define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFUL << MDIOS_CRDFR_CRDF_Pos) /*!< 0xFFFFFFFF */
\r
17982 #define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
\r
17984 /******************** Bit definition for MDIOS_SR register *******************/
\r
17985 #define MDIOS_SR_PERF_Pos (0U)
\r
17986 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
\r
17987 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< Preamble error flag */
\r
17988 #define MDIOS_SR_SERF_Pos (1U)
\r
17989 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
\r
17990 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< Start error flag */
\r
17991 #define MDIOS_SR_TERF_Pos (2U)
\r
17992 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
\r
17993 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< Turnaround error flag */
\r
17995 /******************** Bit definition for MDIOS_CLRFR register *******************/
\r
17996 #define MDIOS_CLRFR_CPERF_Pos (0U)
\r
17997 #define MDIOS_CLRFR_CPERF_Msk (0x1UL << MDIOS_CLRFR_CPERF_Pos) /*!< 0x00000001 */
\r
17998 #define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk /*!< Clear the preamble error flag */
\r
17999 #define MDIOS_CLRFR_CSERF_Pos (1U)
\r
18000 #define MDIOS_CLRFR_CSERF_Msk (0x1UL << MDIOS_CLRFR_CSERF_Pos) /*!< 0x00000002 */
\r
18001 #define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk /*!< Clear the start error flag */
\r
18002 #define MDIOS_CLRFR_CTERF_Pos (2U)
\r
18003 #define MDIOS_CLRFR_CTERF_Msk (0x1UL << MDIOS_CLRFR_CTERF_Pos) /*!< 0x00000004 */
\r
18004 #define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk /*!< Clear the turnaround error flag */
\r
18014 /** @addtogroup Exported_macros
\r
18018 /******************************* ADC Instances ********************************/
\r
18019 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
\r
18020 ((__INSTANCE__) == ADC2) || \
\r
18021 ((__INSTANCE__) == ADC3))
\r
18022 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
\r
18024 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
\r
18026 /******************************* CAN Instances ********************************/
\r
18027 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
\r
18028 ((__INSTANCE__) == CAN2) || \
\r
18029 ((__INSTANCE__) == CAN3))
\r
18030 /******************************* CRC Instances ********************************/
\r
18031 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
\r
18033 /******************************* DAC Instances ********************************/
\r
18034 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
\r
18036 /******************************* DCMI Instances *******************************/
\r
18037 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
\r
18039 /****************************** DFSDM Instances *******************************/
\r
18040 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
\r
18041 ((INSTANCE) == DFSDM1_Filter1) || \
\r
18042 ((INSTANCE) == DFSDM1_Filter2) || \
\r
18043 ((INSTANCE) == DFSDM1_Filter3))
\r
18045 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
\r
18046 ((INSTANCE) == DFSDM1_Channel1) || \
\r
18047 ((INSTANCE) == DFSDM1_Channel2) || \
\r
18048 ((INSTANCE) == DFSDM1_Channel3) || \
\r
18049 ((INSTANCE) == DFSDM1_Channel4) || \
\r
18050 ((INSTANCE) == DFSDM1_Channel5) || \
\r
18051 ((INSTANCE) == DFSDM1_Channel6) || \
\r
18052 ((INSTANCE) == DFSDM1_Channel7))
\r
18054 /******************************* DMA2D Instances *******************************/
\r
18055 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
\r
18057 /******************************** DMA Instances *******************************/
\r
18058 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
\r
18059 ((__INSTANCE__) == DMA1_Stream1) || \
\r
18060 ((__INSTANCE__) == DMA1_Stream2) || \
\r
18061 ((__INSTANCE__) == DMA1_Stream3) || \
\r
18062 ((__INSTANCE__) == DMA1_Stream4) || \
\r
18063 ((__INSTANCE__) == DMA1_Stream5) || \
\r
18064 ((__INSTANCE__) == DMA1_Stream6) || \
\r
18065 ((__INSTANCE__) == DMA1_Stream7) || \
\r
18066 ((__INSTANCE__) == DMA2_Stream0) || \
\r
18067 ((__INSTANCE__) == DMA2_Stream1) || \
\r
18068 ((__INSTANCE__) == DMA2_Stream2) || \
\r
18069 ((__INSTANCE__) == DMA2_Stream3) || \
\r
18070 ((__INSTANCE__) == DMA2_Stream4) || \
\r
18071 ((__INSTANCE__) == DMA2_Stream5) || \
\r
18072 ((__INSTANCE__) == DMA2_Stream6) || \
\r
18073 ((__INSTANCE__) == DMA2_Stream7))
\r
18075 /******************************* GPIO Instances *******************************/
\r
18076 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
\r
18077 ((__INSTANCE__) == GPIOB) || \
\r
18078 ((__INSTANCE__) == GPIOC) || \
\r
18079 ((__INSTANCE__) == GPIOD) || \
\r
18080 ((__INSTANCE__) == GPIOE) || \
\r
18081 ((__INSTANCE__) == GPIOF) || \
\r
18082 ((__INSTANCE__) == GPIOG) || \
\r
18083 ((__INSTANCE__) == GPIOH) || \
\r
18084 ((__INSTANCE__) == GPIOI) || \
\r
18085 ((__INSTANCE__) == GPIOJ) || \
\r
18086 ((__INSTANCE__) == GPIOK))
\r
18088 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
\r
18089 ((__INSTANCE__) == GPIOB) || \
\r
18090 ((__INSTANCE__) == GPIOC) || \
\r
18091 ((__INSTANCE__) == GPIOD) || \
\r
18092 ((__INSTANCE__) == GPIOE) || \
\r
18093 ((__INSTANCE__) == GPIOF) || \
\r
18094 ((__INSTANCE__) == GPIOG) || \
\r
18095 ((__INSTANCE__) == GPIOH) || \
\r
18096 ((__INSTANCE__) == GPIOI) || \
\r
18097 ((__INSTANCE__) == GPIOJ) || \
\r
18098 ((__INSTANCE__) == GPIOK))
\r
18100 /****************************** CEC Instances *********************************/
\r
18101 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
\r
18103 /****************************** QSPI Instances *********************************/
\r
18104 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
\r
18107 /******************************** I2C Instances *******************************/
\r
18108 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
\r
18109 ((__INSTANCE__) == I2C2) || \
\r
18110 ((__INSTANCE__) == I2C3) || \
\r
18111 ((__INSTANCE__) == I2C4))
\r
18113 /****************************** SMBUS Instances *******************************/
\r
18114 #define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
\r
18115 ((__INSTANCE__) == I2C2) || \
\r
18116 ((__INSTANCE__) == I2C3) || \
\r
18117 ((__INSTANCE__) == I2C4))
\r
18120 /******************************** I2S Instances *******************************/
\r
18121 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
\r
18122 ((__INSTANCE__) == SPI2) || \
\r
18123 ((__INSTANCE__) == SPI3))
\r
18125 /******************************* LPTIM Instances ********************************/
\r
18126 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
\r
18128 /****************************** LTDC Instances ********************************/
\r
18129 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
\r
18131 /****************************** MDIOS Instances ********************************/
\r
18132 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
\r
18134 /****************************** MDIOS Instances ********************************/
\r
18135 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
\r
18138 /******************************* RNG Instances ********************************/
\r
18139 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
\r
18141 /****************************** RTC Instances *********************************/
\r
18142 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
\r
18144 /******************************* SAI Instances ********************************/
\r
18145 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
\r
18146 ((__PERIPH__) == SAI1_Block_B) || \
\r
18147 ((__PERIPH__) == SAI2_Block_A) || \
\r
18148 ((__PERIPH__) == SAI2_Block_B))
\r
18149 /* Legacy define */
\r
18150 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
\r
18152 /******************************** SDMMC Instances *******************************/
\r
18153 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
\r
18154 ((__INSTANCE__) == SDMMC2))
\r
18156 /****************************** SPDIFRX Instances *********************************/
\r
18157 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
\r
18159 /******************************** SPI Instances *******************************/
\r
18160 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
\r
18161 ((__INSTANCE__) == SPI2) || \
\r
18162 ((__INSTANCE__) == SPI3) || \
\r
18163 ((__INSTANCE__) == SPI4) || \
\r
18164 ((__INSTANCE__) == SPI5) || \
\r
18165 ((__INSTANCE__) == SPI6))
\r
18167 /****************** TIM Instances : All supported instances *******************/
\r
18168 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18169 ((__INSTANCE__) == TIM2) || \
\r
18170 ((__INSTANCE__) == TIM3) || \
\r
18171 ((__INSTANCE__) == TIM4) || \
\r
18172 ((__INSTANCE__) == TIM5) || \
\r
18173 ((__INSTANCE__) == TIM6) || \
\r
18174 ((__INSTANCE__) == TIM7) || \
\r
18175 ((__INSTANCE__) == TIM8) || \
\r
18176 ((__INSTANCE__) == TIM9) || \
\r
18177 ((__INSTANCE__) == TIM10) || \
\r
18178 ((__INSTANCE__) == TIM11) || \
\r
18179 ((__INSTANCE__) == TIM12) || \
\r
18180 ((__INSTANCE__) == TIM13) || \
\r
18181 ((__INSTANCE__) == TIM14))
\r
18183 /****************** TIM Instances : supporting 32 bits counter ****************/
\r
18184 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
\r
18185 ((__INSTANCE__) == TIM5))
\r
18187 /****************** TIM Instances : supporting the break function *************/
\r
18188 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
18189 ((INSTANCE) == TIM8))
\r
18191 /************** TIM Instances : supporting Break source selection *************/
\r
18192 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
18193 ((INSTANCE) == TIM8))
\r
18195 /****************** TIM Instances : supporting 2 break inputs *****************/
\r
18196 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
18197 ((INSTANCE) == TIM8))
\r
18199 /************* TIM Instances : at least 1 capture/compare channel *************/
\r
18200 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18201 ((__INSTANCE__) == TIM2) || \
\r
18202 ((__INSTANCE__) == TIM3) || \
\r
18203 ((__INSTANCE__) == TIM4) || \
\r
18204 ((__INSTANCE__) == TIM5) || \
\r
18205 ((__INSTANCE__) == TIM8) || \
\r
18206 ((__INSTANCE__) == TIM9) || \
\r
18207 ((__INSTANCE__) == TIM10) || \
\r
18208 ((__INSTANCE__) == TIM11) || \
\r
18209 ((__INSTANCE__) == TIM12) || \
\r
18210 ((__INSTANCE__) == TIM13) || \
\r
18211 ((__INSTANCE__) == TIM14))
\r
18213 /************ TIM Instances : at least 2 capture/compare channels *************/
\r
18214 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18215 ((__INSTANCE__) == TIM2) || \
\r
18216 ((__INSTANCE__) == TIM3) || \
\r
18217 ((__INSTANCE__) == TIM4) || \
\r
18218 ((__INSTANCE__) == TIM5) || \
\r
18219 ((__INSTANCE__) == TIM8) || \
\r
18220 ((__INSTANCE__) == TIM9) || \
\r
18221 ((__INSTANCE__) == TIM12))
\r
18223 /************ TIM Instances : at least 3 capture/compare channels *************/
\r
18224 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18225 ((__INSTANCE__) == TIM2) || \
\r
18226 ((__INSTANCE__) == TIM3) || \
\r
18227 ((__INSTANCE__) == TIM4) || \
\r
18228 ((__INSTANCE__) == TIM5) || \
\r
18229 ((__INSTANCE__) == TIM8))
\r
18231 /************ TIM Instances : at least 4 capture/compare channels *************/
\r
18232 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18233 ((__INSTANCE__) == TIM2) || \
\r
18234 ((__INSTANCE__) == TIM3) || \
\r
18235 ((__INSTANCE__) == TIM4) || \
\r
18236 ((__INSTANCE__) == TIM5) || \
\r
18237 ((__INSTANCE__) == TIM8))
\r
18239 /****************** TIM Instances : at least 5 capture/compare channels *******/
\r
18240 #define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18241 ((__INSTANCE__) == TIM8))
\r
18243 /****************** TIM Instances : at least 6 capture/compare channels *******/
\r
18244 #define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18245 ((__INSTANCE__) == TIM8))
\r
18247 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
\r
18248 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18249 ((__INSTANCE__) == TIM8))
\r
18251 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
\r
18252 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18253 ((__INSTANCE__) == TIM8) || \
\r
18254 ((__INSTANCE__) == TIM2) || \
\r
18255 ((__INSTANCE__) == TIM3) || \
\r
18256 ((__INSTANCE__) == TIM4) || \
\r
18257 ((__INSTANCE__) == TIM5) || \
\r
18258 ((__INSTANCE__) == TIM6) || \
\r
18259 ((__INSTANCE__) == TIM7))
\r
18261 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
\r
18262 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18263 ((__INSTANCE__) == TIM2) || \
\r
18264 ((__INSTANCE__) == TIM3) || \
\r
18265 ((__INSTANCE__) == TIM4) || \
\r
18266 ((__INSTANCE__) == TIM5) || \
\r
18267 ((__INSTANCE__) == TIM8))
\r
18269 /******************** TIM Instances : DMA burst feature ***********************/
\r
18270 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18271 ((__INSTANCE__) == TIM2) || \
\r
18272 ((__INSTANCE__) == TIM3) || \
\r
18273 ((__INSTANCE__) == TIM4) || \
\r
18274 ((__INSTANCE__) == TIM5) || \
\r
18275 ((__INSTANCE__) == TIM8))
\r
18277 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
\r
18278 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
\r
18279 (((__INSTANCE__) == TIM1) || \
\r
18280 ((__INSTANCE__) == TIM8))
\r
18282 /****************** TIM Instances : supporting counting mode selection ********/
\r
18283 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18284 ((__INSTANCE__) == TIM2) || \
\r
18285 ((__INSTANCE__) == TIM3) || \
\r
18286 ((__INSTANCE__) == TIM4) || \
\r
18287 ((__INSTANCE__) == TIM5) || \
\r
18288 ((__INSTANCE__) == TIM8))
\r
18290 /****************** TIM Instances : supporting encoder interface **************/
\r
18291 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18292 ((__INSTANCE__) == TIM2) || \
\r
18293 ((__INSTANCE__) == TIM3) || \
\r
18294 ((__INSTANCE__) == TIM4) || \
\r
18295 ((__INSTANCE__) == TIM5) || \
\r
18296 ((__INSTANCE__) == TIM8))
\r
18298 /****************** TIM Instances : supporting OCxREF clear *******************/
\r
18299 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
\r
18300 (((__INSTANCE__) == TIM2) || \
\r
18301 ((__INSTANCE__) == TIM3) || \
\r
18302 ((__INSTANCE__) == TIM4) || \
\r
18303 ((__INSTANCE__) == TIM5))
\r
18305 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
\r
18306 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
\r
18307 (((__INSTANCE__) == TIM1) || \
\r
18308 ((__INSTANCE__) == TIM2) || \
\r
18309 ((__INSTANCE__) == TIM3) || \
\r
18310 ((__INSTANCE__) == TIM4) || \
\r
18311 ((__INSTANCE__) == TIM5) || \
\r
18312 ((__INSTANCE__) == TIM8))
\r
18314 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
\r
18315 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
\r
18316 (((__INSTANCE__) == TIM1) || \
\r
18317 ((__INSTANCE__) == TIM2) || \
\r
18318 ((__INSTANCE__) == TIM3) || \
\r
18319 ((__INSTANCE__) == TIM4) || \
\r
18320 ((__INSTANCE__) == TIM5) || \
\r
18321 ((__INSTANCE__) == TIM8))
\r
18323 /******************** TIM Instances : Advanced-control timers *****************/
\r
18324 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18325 ((__INSTANCE__) == TIM8))
\r
18327 /******************* TIM Instances : Timer input XOR function *****************/
\r
18328 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18329 ((__INSTANCE__) == TIM2) || \
\r
18330 ((__INSTANCE__) == TIM3) || \
\r
18331 ((__INSTANCE__) == TIM4) || \
\r
18332 ((__INSTANCE__) == TIM5) || \
\r
18333 ((__INSTANCE__) == TIM8))
\r
18335 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
\r
18336 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18337 ((__INSTANCE__) == TIM2) || \
\r
18338 ((__INSTANCE__) == TIM3) || \
\r
18339 ((__INSTANCE__) == TIM4) || \
\r
18340 ((__INSTANCE__) == TIM5) || \
\r
18341 ((__INSTANCE__) == TIM6) || \
\r
18342 ((__INSTANCE__) == TIM7) || \
\r
18343 ((__INSTANCE__) == TIM8))
\r
18345 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
\r
18346 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18347 ((__INSTANCE__) == TIM2) || \
\r
18348 ((__INSTANCE__) == TIM3) || \
\r
18349 ((__INSTANCE__) == TIM4) || \
\r
18350 ((__INSTANCE__) == TIM5) || \
\r
18351 ((__INSTANCE__) == TIM8) || \
\r
18352 ((__INSTANCE__) == TIM9) || \
\r
18353 ((__INSTANCE__) == TIM12))
\r
18355 /***************** TIM Instances : external trigger input available ************/
\r
18356 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18357 ((__INSTANCE__) == TIM2) || \
\r
18358 ((__INSTANCE__) == TIM3) || \
\r
18359 ((__INSTANCE__) == TIM4) || \
\r
18360 ((__INSTANCE__) == TIM5) || \
\r
18361 ((__INSTANCE__) == TIM8))
\r
18363 /****************** TIM Instances : remapping capability **********************/
\r
18364 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
\r
18365 ((__INSTANCE__) == TIM5) || \
\r
18366 ((__INSTANCE__) == TIM11))
\r
18368 /******************* TIM Instances : output(s) available **********************/
\r
18369 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
\r
18370 ((((__INSTANCE__) == TIM1) && \
\r
18371 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18372 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18373 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
18374 ((__CHANNEL__) == TIM_CHANNEL_4) || \
\r
18375 ((__CHANNEL__) == TIM_CHANNEL_5) || \
\r
18376 ((__CHANNEL__) == TIM_CHANNEL_6))) \
\r
18378 (((__INSTANCE__) == TIM2) && \
\r
18379 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18380 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18381 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
18382 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
18384 (((__INSTANCE__) == TIM3) && \
\r
18385 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18386 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18387 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
18388 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
18390 (((__INSTANCE__) == TIM4) && \
\r
18391 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18392 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18393 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
18394 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
18396 (((__INSTANCE__) == TIM5) && \
\r
18397 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18398 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18399 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
18400 ((__CHANNEL__) == TIM_CHANNEL_4))) \
\r
18402 (((__INSTANCE__) == TIM8) && \
\r
18403 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18404 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18405 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
18406 ((__CHANNEL__) == TIM_CHANNEL_4) || \
\r
18407 ((__CHANNEL__) == TIM_CHANNEL_5) || \
\r
18408 ((__CHANNEL__) == TIM_CHANNEL_6))) \
\r
18410 (((__INSTANCE__) == TIM9) && \
\r
18411 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18412 ((__CHANNEL__) == TIM_CHANNEL_2))) \
\r
18414 (((__INSTANCE__) == TIM10) && \
\r
18415 (((__CHANNEL__) == TIM_CHANNEL_1))) \
\r
18417 (((__INSTANCE__) == TIM11) && \
\r
18418 (((__CHANNEL__) == TIM_CHANNEL_1))) \
\r
18420 (((__INSTANCE__) == TIM12) && \
\r
18421 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18422 ((__CHANNEL__) == TIM_CHANNEL_2))) \
\r
18424 (((__INSTANCE__) == TIM13) && \
\r
18425 (((__CHANNEL__) == TIM_CHANNEL_1))) \
\r
18427 (((__INSTANCE__) == TIM14) && \
\r
18428 (((__CHANNEL__) == TIM_CHANNEL_1))))
\r
18430 /************ TIM Instances : complementary output(s) available ***************/
\r
18431 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
\r
18432 ((((__INSTANCE__) == TIM1) && \
\r
18433 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18434 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18435 ((__CHANNEL__) == TIM_CHANNEL_3))) \
\r
18437 (((__INSTANCE__) == TIM8) && \
\r
18438 (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
18439 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
18440 ((__CHANNEL__) == TIM_CHANNEL_3))))
\r
18442 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
\r
18443 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
\r
18444 (((__INSTANCE__) == TIM1) || \
\r
18445 ((__INSTANCE__) == TIM8) )
\r
18447 /****************** TIM Instances : supporting synchronization ****************/
\r
18448 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
\r
18449 (((__INSTANCE__) == TIM1) || \
\r
18450 ((__INSTANCE__) == TIM2) || \
\r
18451 ((__INSTANCE__) == TIM3) || \
\r
18452 ((__INSTANCE__) == TIM4) || \
\r
18453 ((__INSTANCE__) == TIM5) || \
\r
18454 ((__INSTANCE__) == TIM6) || \
\r
18455 ((__INSTANCE__) == TIM7) || \
\r
18456 ((__INSTANCE__) == TIM8))
\r
18458 /****************** TIM Instances : supporting clock division *****************/
\r
18459 #define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18460 ((__INSTANCE__) == TIM2) || \
\r
18461 ((__INSTANCE__) == TIM3) || \
\r
18462 ((__INSTANCE__) == TIM4) || \
\r
18463 ((__INSTANCE__) == TIM5) || \
\r
18464 ((__INSTANCE__) == TIM8) || \
\r
18465 ((__INSTANCE__) == TIM9) || \
\r
18466 ((__INSTANCE__) == TIM10) || \
\r
18467 ((__INSTANCE__) == TIM11) || \
\r
18468 ((__INSTANCE__) == TIM12) || \
\r
18469 ((__INSTANCE__) == TIM13) || \
\r
18470 ((__INSTANCE__) == TIM14))
\r
18472 /****************** TIM Instances : supporting repetition counter *************/
\r
18473 #define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18474 ((__INSTANCE__) == TIM8))
\r
18476 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
\r
18477 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18478 ((__INSTANCE__) == TIM2) || \
\r
18479 ((__INSTANCE__) == TIM3) || \
\r
18480 ((__INSTANCE__) == TIM4) || \
\r
18481 ((__INSTANCE__) == TIM5) || \
\r
18482 ((__INSTANCE__) == TIM8) || \
\r
18483 ((__INSTANCE__) == TIM9) || \
\r
18484 ((__INSTANCE__) == TIM12))
\r
18486 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
\r
18487 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18488 ((__INSTANCE__) == TIM2) || \
\r
18489 ((__INSTANCE__) == TIM3) || \
\r
18490 ((__INSTANCE__) == TIM4) || \
\r
18491 ((__INSTANCE__) == TIM5) || \
\r
18492 ((__INSTANCE__) == TIM8))
\r
18494 /****************** TIM Instances : supporting Hall sensor interface **********/
\r
18495 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18496 ((__INSTANCE__) == TIM2) || \
\r
18497 ((__INSTANCE__) == TIM3) || \
\r
18498 ((__INSTANCE__) == TIM4) || \
\r
18499 ((__INSTANCE__) == TIM5) || \
\r
18500 ((__INSTANCE__) == TIM8))
\r
18502 /****************** TIM Instances : supporting commutation event generation ***/
\r
18503 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
18504 ((__INSTANCE__) == TIM8))
\r
18506 /******************** USART Instances : Synchronous mode **********************/
\r
18507 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18508 ((__INSTANCE__) == USART2) || \
\r
18509 ((__INSTANCE__) == USART3) || \
\r
18510 ((__INSTANCE__) == USART6))
\r
18512 /******************** UART Instances : Asynchronous mode **********************/
\r
18513 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18514 ((__INSTANCE__) == USART2) || \
\r
18515 ((__INSTANCE__) == USART3) || \
\r
18516 ((__INSTANCE__) == UART4) || \
\r
18517 ((__INSTANCE__) == UART5) || \
\r
18518 ((__INSTANCE__) == USART6) || \
\r
18519 ((__INSTANCE__) == UART7) || \
\r
18520 ((__INSTANCE__) == UART8))
\r
18522 /****************** UART Instances : Auto Baud Rate detection ****************/
\r
18523 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18524 ((__INSTANCE__) == USART2) || \
\r
18525 ((__INSTANCE__) == USART3) || \
\r
18526 ((__INSTANCE__) == USART6))
\r
18528 /****************** UART Instances : Driver Enable *****************/
\r
18529 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18530 ((__INSTANCE__) == USART2) || \
\r
18531 ((__INSTANCE__) == USART3) || \
\r
18532 ((__INSTANCE__) == UART4) || \
\r
18533 ((__INSTANCE__) == UART5) || \
\r
18534 ((__INSTANCE__) == USART6) || \
\r
18535 ((__INSTANCE__) == UART7) || \
\r
18536 ((__INSTANCE__) == UART8))
\r
18538 /******************** UART Instances : Half-Duplex mode **********************/
\r
18539 #define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18540 ((__INSTANCE__) == USART2) || \
\r
18541 ((__INSTANCE__) == USART3) || \
\r
18542 ((__INSTANCE__) == UART4) || \
\r
18543 ((__INSTANCE__) == UART5) || \
\r
18544 ((__INSTANCE__) == USART6) || \
\r
18545 ((__INSTANCE__) == UART7) || \
\r
18546 ((__INSTANCE__) == UART8))
\r
18548 /****************** UART Instances : Hardware Flow control ********************/
\r
18549 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18550 ((__INSTANCE__) == USART2) || \
\r
18551 ((__INSTANCE__) == USART3) || \
\r
18552 ((__INSTANCE__) == UART4) || \
\r
18553 ((__INSTANCE__) == UART5) || \
\r
18554 ((__INSTANCE__) == USART6) || \
\r
18555 ((__INSTANCE__) == UART7) || \
\r
18556 ((__INSTANCE__) == UART8))
\r
18558 /******************** UART Instances : LIN mode **********************/
\r
18559 #define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18560 ((__INSTANCE__) == USART2) || \
\r
18561 ((__INSTANCE__) == USART3) || \
\r
18562 ((__INSTANCE__) == UART4) || \
\r
18563 ((__INSTANCE__) == UART5) || \
\r
18564 ((__INSTANCE__) == USART6) || \
\r
18565 ((__INSTANCE__) == UART7) || \
\r
18566 ((__INSTANCE__) == UART8))
\r
18568 /********************* UART Instances : Smart card mode ***********************/
\r
18569 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18570 ((__INSTANCE__) == USART2) || \
\r
18571 ((__INSTANCE__) == USART3) || \
\r
18572 ((__INSTANCE__) == USART6))
\r
18574 /*********************** UART Instances : IRDA mode ***************************/
\r
18575 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
\r
18576 ((__INSTANCE__) == USART2) || \
\r
18577 ((__INSTANCE__) == USART3) || \
\r
18578 ((__INSTANCE__) == UART4) || \
\r
18579 ((__INSTANCE__) == UART5) || \
\r
18580 ((__INSTANCE__) == USART6) || \
\r
18581 ((__INSTANCE__) == UART7) || \
\r
18582 ((__INSTANCE__) == UART8))
\r
18584 /****************************** IWDG Instances ********************************/
\r
18585 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
\r
18587 /****************************** WWDG Instances ********************************/
\r
18588 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
\r
18590 /*********************** PCD Instances ****************************************/
\r
18591 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
\r
18592 ((INSTANCE) == USB_OTG_HS))
\r
18594 /*********************** HCD Instances ****************************************/
\r
18595 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
\r
18596 ((INSTANCE) == USB_OTG_HS))
\r
18598 /******************************************************************************/
\r
18599 /* For a painless codes migration between the STM32F7xx device product */
\r
18600 /* lines, the aliases defined below are put in place to overcome the */
\r
18601 /* differences in the interrupt handlers and IRQn definitions. */
\r
18602 /* No need to update developed interrupt code when moving across */
\r
18603 /* product lines within the same STM32F7 Family */
\r
18604 /******************************************************************************/
\r
18606 /* Aliases for __IRQn */
\r
18607 #define HASH_RNG_IRQn RNG_IRQn
\r
18609 /* Aliases for __IRQHandler */
\r
18610 #define HASH_RNG_IRQHandler RNG_IRQHandler
\r
18624 #ifdef __cplusplus
\r
18626 #endif /* __cplusplus */
\r
18628 #endif /* __STM32F767xx_H */
\r
18631 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
projects / pioneer-stm32 / blob